LTC2448_15 Datasheet, PDF (20/28 Pages) Linear Technology – 24-Bit High Speed 8-/16-Channel ADCs with Selectable Speed/Resolution

LTC2444/LTC2445/
LTC2448/LTC2449
APPLICATIO S I FOR ATIO
If CS remains LOW longer than t_EOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 8. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. Thirteen
serial input data bits are required in order to properly
program the speed/resolution and input channel. If the
data output sequence is aborted prior to the 13th rising
edge of SCK, the new input data is ignored, and the
previously selected speed/resolution and channel are used
for the next conversion cycle. If a new channel is being
programmed, the rising edge of CS must come after the
14th falling edge of SCK in order to store the data input
sequence.
4.5V TO 5.5V
1µF
28
V_CC
35
F_O
LTC2448
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
REFERENCE ²⁹ _REF⁺
VOLTAGE
0.1V TO V_CC
30 _REF–
8 _CH0
••• ₁₅
•••
CH7
ANALOG
INPUTS
16
CH8
••• ₂₃
•••
CH15
7
COM
34
SDI
38
SCK
4-WIRE
SDO ³⁷
SPI INTERFACE
36
CS
2
BUSY
1,4,5,6,31,32,33,39
GND
<t_EOC(TEST)
CS
<t_EOC(TEST)
1
5
SCK
1
2
3
4
5
6
TEST EOC
SDI
DON'T CARE
DON'T CARE
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25
Hi-Z
Hi-Z
SDO
EOC “0” SIG MSB
DON'T CARE
BUSY
CONVERSION
DATA OUTPUT
SLEEP
CONVERSION
DATA OUTPUT
CONVERSION
Figure 8. Internal Serial Clock, Reduced Data Output Length
20
SLEEP
2444 F09
2444589fb