LTC2435-1_15 Datasheet, PDF (20/42 Pages) Linear Technology – 20-Bit No Latency ADCs with Differential Input and Differential Reference

LTC2435/LTC2435-1
applications information
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pull-
ing CS HIGH anytime between the first rising edge and
the 24th falling edge of SCK, see Figure 9. On the rising
edge of CS, the device aborts the data output state and
immediately initiates a new conversion. This is useful for
systems not requiring all 24 bits of output data, aborting
an invalid conversion cycle or synchronizing the start of
a conversion.
2.7V TO 5.5V
1µF
2 _VCC
F_O ¹⁴
REFERENCE
VOLTAGE
0.1V TO V_CC
LTC2435/
LTC2435-1
3 _REF+
4 _REF–
SCK ¹³
ANALOG INPUT RANGE ⁵ _IN+
–0.5V_REF TO 0.5V_REF
6 _IN–
1, 7, 8, 9, 10, 15, 16 _GND
SDO ¹²
CS ¹¹
V_CC
= 50Hz REJECTION (LTC2435)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2435)
= 50Hz/60Hz REJECTION (LTC2435-1)
3-WIRE
SPI INTERFACE
CS
BIT 0
TEST EOC
SDO
EOC
Hi-Z
Hi-Z
SCK
(EXTERNAL)
SLEEP
DATA OUTPUT
CONVERSION
SLEEP
TEST EOC
BIT 23
EOC
Hi-Z
BIT 22
SLEEP
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 9
BIT 8
TEST EOC
Hi-Z
DATA OUTPUT
CONVERSION
2435 F09
Figure 9. External Serial Clock, Reduced Data Output Length
20
For more information www.linear.com/LTC2435
24351fc