LTC2430 Datasheet, PDF (20/40 Pages) Linear Technology – 20-Bit No Latency Delta-Sigma ADCs with Differential Input and Differential Reference

LTC2430/LTC2431
APPLICATIO S I FOR ATIO
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2430/LTC2431’s internal
pull-up at pin SCK is disabled. Normally, SCK is not exter-
nally driven if the device is in the internal SCK timing mode.
However, certain applications may require an external
driver on SCK. If this driver goes Hi-Z after outputting a LOW
signal, the LTC2430/LTC2431’s internal pull-up remains
disabled. Hence, SCK remains LOW. On the next falling
edge of CS, the device is switched to the external SCK timing
mode. By adding an external 10k pull-up resistor to SCK,
this pin goes HIGH once the external driver goes Hi-Z. On
the next CS falling edge, the device will remain in the in-
ternal SCK timing mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
period defined above as t_EOCtest), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground, simpli-
fying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after V_CC exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
2.7V TO 5.5V
1µF
REFERENCE
VOLTAGE
0.1V TO V_CC
V_CC
F_O
LTC2430/
LTC2431
REF⁺
SCK
REF^–
ANALOG INPUT RANGE
–0.5V_REF TO 0.5V_REF
IN⁺
SDO
IN^–
CS
GND
V_CC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
2-WIRE I/O
CS
BIT 23 BIT 22
BIT 21
BIT 20
BIT 19
BIT 18
BIT 0
SDO
EOC
SIG
MSB
LSB
SCK
(INTERNAL)
CONVERSION
20
DATA OUTPUT
Figure 10. Internal Serial Clock, CS = 0 Continuous Operation
CONVERSION
2431 F10
24301f