RH1011_15 Datasheet, PDF (2/2 Pages) Linear Technology – Voltage Comparator

DICE SPECIFICATION
RH1011
W
DICE ELECTRICAL TEST LI ITS V_S = ±15V, V_CM = 0V, R_S = 0Ω, T_J = 25°C, V_GND = V^–
SYMBOL PARAMETER
V_OS
Input Offset Voltage
I_OS
Input Offset Current
I_B
Input Bias Current
A_VOL
Large-Signal Voltage Gain
CMRR
Common Mode Rejection Ratio
Input Voltage Range
V_OL
Output Saturation Voltage
Output Leakage Current
Positive Supply Current
CONDITIONS
(Note 2)
R_S ≤ 50k (Note 3)
(Note 3)
(Note 2)
(Note 3)
V_S = ±15V, R_L = 1k, –10V ≤ V_OUT ≤ 14.5V
V_S = 5V, R_L = 500Ω , 0.5V ≤ V_OUT ≤ 4.5V
V_S = ±15V
V_S = Single 5V
V_IN– = 5mV, V_GND = 0V, I_SINK = 8mA
I_SINK = 50mA
V_IN+ = 5mV, V_GND = –15V
V_OUT = 20V
(Note 4)
MIN
200
50
90
–14.5
0.5
MAX
UNITS
1.5
mV
2.0
mV
4
nA
50
nA
65
nA
V/mV
V/mV
dB
13
V
3
V
0.4
V
1.5
V
10
nA
4
mA
Negative Supply Current
Strobe Current
(Note 4)
Minimum to Ensure Output Transistor Is Off (Notes 4, 5, 6)
2.5
mA
500
µA
Note 1: Absolute Maximum Ratings are those values beyond which the
life of a device may be impaired.
Note 2: Output is sinking 1.5mA with V_OUT = 0V.
Note 3: These specifications apply for all supply voltages from a single
5V to ±15V, the entire input voltage range and for both high and low
output states. The high state is I_SINK ≥ 100µA, V_OUT ≥ (V⁺ – 1V) and
the low state is I_SINK ≤ 8mA, V_OUT ≤ 0.8V. Therefore, this specification
defines a worst-case error band that includes effects due to common
mode signals, voltage gain and output load.
Note 4: V_GND = 0V
Note 5: Do not short the STROBE pad to ground. It should be current
driven at 3mA to 5mA for the shortest strobe time. Currents as low as
500µA will strobe the RH1011 if speed is not important. External
leakage on the STROBE pin in excess of 0.2µA when the strobe is “off”
can cause offset voltage shifts.
Note 6: Guaranteed by design, characterization or correlation to other
tested parameters.
Note 7: Please refer to LTC standard product data sheets for all other
applicable information.
Rad Hard die require special handling as compared to standard IC
chips.
Rad Hard die are susceptible to surface damage because there is no
silicon nitride passivation as on standard die. Silicon nitride protects
the die surface from scratches by its hard and dense properties. The
passivation on Rad Hard die is silicon dioxide that is much “softer”
than silicon nitride.
LTC recommends that die handling be performed with extreme care so
as to protect the die surface from scratches. If the need arises to move
the die around from the chip tray, use a Teflon-tipped vacuum wand.
This wand can be made by pushing a small diameter Teflon tubing
onto the tip of a steel-tipped wand. The inside diameter of the Teflon
tip should match the die size for efficient pickup. The tip of the Teflon
should be cut square and flat to ensure good vacuum to die surface.
Ensure the Teflon tip remains clean from debris by inspecting under
stereoscope.
During die attach, care must be exercised to ensure no tweezers touch
the top of the die.
Wafer level testing is performed per the indicated specifications for dice. Considerable differences in performance can often be observed for dice versus
packaged units due to the influences of packaging and assembly on certain devices and/or parameters. Please consult factory for more information on
dice performance and lot qualifications via lot sampling test procedures.
Dice data sheet subject to change. Please consult factory for current revision in production.
I.D.No. 66-13-1011
2
Linear Technology Corporation
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LT/LT 0603 REV B • PRINTED IN USA
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