LTC3720 Datasheet, PDF (19/24 Pages) Linear Technology – Single Phase VRM8.5 Current Mode Step-Down Controller

LTC3720
APPLICATIO S I FOR ATIO
However, a 0A to 15A load step will cause an output
change of up to:
∆V_OUT(STEP) = ∆I_LOAD (ESR) = (15A) (0.005Ω) = 75mV
The complete circuit is shown in Figure 7.
Active Voltage Positioning
Active voltage positioning (also termed load “deregula-
tion” or droop) describes a technique where the output
voltage varies with load in a controlled manner. It is useful
in applications where rapid load steps are the main cause
of error in the output voltage. By positioning the output
voltage above the regulation point at zero load, and below
the regulation point at full load, one can use more of the
error budget for the load step. This allows one to reduce
the number of output capacitors by relaxing the ESR
requirement.
In the design example, Figure 7, five 0.025Ω capacitors
are required in parallel to keep the output voltage within
tolerance. Using active voltage positioning, the same
specification can be met with only three capacitors. In this
case, the load step will cause an output voltage change of:
( ) ( ) ^∆VOUT(STEP) ⁼
15A
 ₁
 3
0.025Ω
= 125mV
INT V_CC
100k
POWER GOOD
1
RUN/SS
28
BOOST
C_SS
0.1µF
2
V_ON
3
PGOOD
27
TG
26
SW
C_C2
100pF
R_C 20k
INT V_CC
C_C1 500pF
4
V_RNG
25
SENSE⁺
5
FCB
24
SENSE^–
6
I_TH
23
PGND
7
LTC3720
22
SGND
BG
C_ION
0.01µF
330k
V_IN
C_FB 100pF
C2 6.8nF
8
I_ON
9
V_FB
10
SGND
11
V_FB
12
V_OSENSE
21
INTV_CC
20
V_IN
19
EXTV_CC
18
V_CC
17
VID4
13
VID0
16
VID3
14
VID1
15
VID2
V_IN
7V TO 24V
R_F
10Ω
C_B 0.33µF
M1
IRF7811A
C_IN
10µF
50V
×3
D_B
CMDSH-3
L1
1µH
UPS840
V_OUT
1.05V TO 1.825V
15A
M2
IRF7811A
×2
1Ω
4.7µF
6.3V
C_F
0.1µF
+ ^COUT
270µF
2V
×5
SGND
3720 F07
Figure 7. 15A CPU Core Voltage Regulator at 300kHz
3720f
19