LTC2978A_15 Datasheet, PDF (19/82 Pages) Linear Technology – 8-Channel PMBus Power System Manager Featuring Accurate Output Voltage Measurement

LTC2978A
OPERATION
Nondestructive operation above T_J = 85°C is possible
although the Electrical Characteristics are not guaranteed
and the EEPROM will be degraded.
Operating the EEPROM above 85°C may result in a deg-
radation of retention characteristics. The fault logging
function, which is useful in debugging system problems
that may occur at high temperatures, only writes to fault
log EEPROM locations. If occasional writes to these reg-
isters occur above 85°C, a slight degradation in the data
retention characteristics of the fault log may occur.
It is recommended that the EEPROM not be written using
STORE_USER_ALL or bulk programming when T_J > 85°C.
The degradation in EEPROM retention for temperatures
>85°C can be approximated by calculating the dimension-
less acceleration factor using the following equation.
AF
=
_Ea

e^{}
k



•



T_USE
1
+
273
−
1
T_STRESS
+
273



Where:
AF = acceleration factor
Ea = activation energy = 1.4 eV
k = 8.625×10^−5 eV/°K
T_USE = 85°C specified junction temperature
T_STRESS = actual junction temperature °C
Example: Calculate the effect on retention when operating
at a junction temperature of 95°C for 10 hours.
T_STRESS = 95°C
T_USE = 85°C
AF = 3.4
Equivalent operating time at 85°C = 34 hours.
So the overall retention of the EEPROM was degraded by
34 hours as a result of operation at a junction temperature
of 95°C for 10 hours. Note that the effect of this overstress
is negligible when compared to the overall EEPROM
retention rating of 87,600 hours at a maximum junction
temperature of 85°C.
RESET
Holding the WDI/RESETB pin low for more than t_RESETB
will cause the LTC2978A to enter the power-on reset
state. While in the power-on reset state, the device will not
communicate on the I²C bus. Following the subsequent
rising-edge of the WDI/RESETB pin, the LTC2978A will
execute its power-on sequence per the user configuration
stored in EEPROM. Connect WDI/RESETB to VDD33 with
a 10k resistor. WDI/RESETB includes an internal 256µs
deglitch filter so additional filter capacitance on this pin
is not recommended.
WRITE-PROTECT PIN
The WP pin allows the user to write-protect the LTC2978A’s
configuration registers. The WP pin is active high, and
when asserted it provides Level 2 protection: all writes are
disabled except to the WRITE_PROTECT, PAGE, STORE_
USER_ALL, OPERATION, MFR_PAGE_FF_MASK and
CLEAR_FAULTS commands. The most restrictive setting
between the WP pin and WRITE_PROTECT command will
override. For example if WP = 1 and WRITE_PROTECT =
0x80, then the WRITE_PROTECT command overrides,
since it is the most restrictive.
OTHER OPERATIONS
Clock Sharing
Multiple LTC PMBus devices can synchronize their clocks
in an application by connecting together the open-drain
SHARE_CLK input/outputs to a pull-up resistor as a wired
OR. In this case the fastest clock will take over and syn-
chronize all LTC2978As.
SHARE_CLK can optionally be used to synchronize ON/OFF
dependency on V_IN across multiple chips by setting the
Mfr_config_all_vin_share_enable bit of the MFR_CONFIG_
ALL_LTC2978 register. When configured this way the chip
will hold SHARE_CLK low when the unit is off for insufficient
input voltage, and upon detecting that SHARE_CLK is held
low the chip will disable all channels after a brief deglitch
period. When the SHARE_CLK pin is allowed to rise, the
For more information www.linear.com/LTC2978A
2978afa
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