LTC2442_15 Datasheet, PDF (19/32 Pages) Linear Technology – 24-Bit High Speed 4-Channel ADC with Integrated Amplifier

LTC2442
Applications Information
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift
out the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 7.
In order to select the internal serial clock timing mode,
the EXT pin must be tied HIGH.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state. Alterna-
tively, BUSY (Pin 2) may be used to monitor the status
of the conversion in progress. BUSY is HIGH during the
conversion and goes LOW at the conclusion. It remains
LOW until the result is read from the device.
When testing EOC, if the conversion is complete (EOC =
0), the device will exit the sleep state and enter the data
output state if CS remains LOW. In order to prevent the
device from exiting the sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t_EOCtest after the falling edge of CS
(if EOC = 0) or t_EOCtest after EOC goes LOW (if CS is LOW
during the falling edge of EOC). The value of t_EOCtest is
500ns. If CS is pulled HIGH before time t_EOCtest, the device
remains in the sleep state. The conversion result is held
in the internal static shift register.
<t_EOC(TEST)
4.5V TO 5.5V
V_CC TO 15V
1µF
29 _VCC
1µF
V^{+ 21}
LTC2442
REFERENCE
VOLTAGE
0.1V TO V_CC
30 _REF+
31 _REF–
ANALOG
INPUTS
6
CH0
7
CH1
8
CH2
9
CH3
28
COM
EXT
3
V_CC
SDI ³³
SCK ¹
SDO ³⁶
4-WIRE
SPI INTERFACE
CS ³⁵
F_O ³⁴
2
BUSY
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
(SIMULTANEOUS 50Hz/60Hz
REJECTION AT 6.9Hz OUTPUT RATE
0.1µF
0.1µF
12
13
11
OUTA
MUXOUTA
–INA
+INA
ADCINA
27
25
26
MUXOUTB
17 _OUTB
+INB ¹⁹
18 _–INB
10
ADCINB
V^{– 24} –15V TO GND
4, 5, 32
GND
CS
TEST EOC
TEST EOC
1
2
3
4
5
6
7
8
9
10 11 12 13 14
32
SCK
SDI
DON'T CARE
1
0
EN SGL ODD 0
0
A0 OSR3 OSR2 OSR1 OSR0 TWOX
DON'T CARE
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19
BIT 0
Hi-Z
SDO
EOC “0” SIG MSB
LSB
Hi-Z
BUSY
CONVERSION
SLEEP
DATA OUTPUT
Figure 7. Internal Serial Clock, Single Cycle Operation
For more information www.linear.com/LTC2442
CONVERSION
2442 F07
2442fa
19