LTC2414_15 Datasheet, PDF (19/48 Pages) Linear Technology – 8-/16-Channel 24-Bit No Latency ADCs

LTC2414/LTC2418
APPLICATIO S I FOR ATIO
last input bit A0 of SDI by the time CS pulled HIGH, the
address information is discarded and the previous
address is kept.
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by F_O.
SERIAL INTERFACE TIMING MODES
The LTC2414/LTC2418’s 4-wire interface is SPI and
MICROWIRE compatible. This interface offers several
flexible modes of operation. These include internal/exter-
nal serial clock, 3- or 4-wire I/O, single cycle conversion.
The following sections describe each of these serial inter-
face timing modes in detail. In all these cases, the con-
verter can use the internal oscillator (F_O = LOW or F_O =
HIGH) or an external oscillator connected to the F_O pin.
Refer to Table 6 for a summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.
Table 6. LTC2414/LTC2418 Interface Timing Modes
Configuration
External SCK, Single Cycle Conversion
External SCK, 3-Wire I/O
Internal SCK, Single Cycle Conversion
Internal SCK, 3-Wire I/O, Continuous Conversion
SCK
Source
External
External
Internal
Internal
Conversion
Cycle
Control
CS and SCK
SCK
CS ↓
Continuous
Data
Output
Control
CS and SCK
SCK
CS ↓
Internal
Connection
and
Waveforms
Figures 5, 6
Figure 7
Figures 8, 9
Figure 10
TEST EOC
(OPTIONAL)
CS
TEST EOC
SDO
Hi-Z
Hi-Z
SCK
(EXTERNAL)
SDI
DON’T CARE
CONVERSION
SLEEP
SLEEP
2.7V TO 5.5V
1µF
9
V_CC
19
F_O
LTC2414/
LTC2418
REFERENCE ¹¹ _REF⁺
VOLTAGE
0.1V TO V_CC
12 _REF–
21
CH0
••• ₂₈
•••
CH7
20
SDI
SCK ¹⁸
17
SDO
ANALOG
INPUTS
1
CH8
••• ₈
•••
CH15
CS ¹⁶
10
COM
15
GND
V_CC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
4-WIRE
SPI INTERFACE
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 25
BIT 24
BIT 6
LSB
(1)
(0)
EN
SGL
ODD/
SIGN
A2
A1
A0
DATA OUTPUT
DON’T CARE
Figure 5. External Serial Clock, Single Cycle Operation
BIT 0
PARITY
TEST EOC
Hi-Z
CONVERSION
241418 F05
241418fa
19