LTC2323-12_15 Datasheet, PDF (19/24 Pages) Linear Technology – Dual, 12-Bit + Sign, 5Msps Differential Input ADC with Wide Input Common Mode Range

LTC2323-12
Applications Information
TIMING AND CONTROL
CNV Timing
The LTC2323-12 sampling and conversion is controlled
by CNV. A rising edge on CNV will start sampling and the
falling edge starts the conversion and readout process. The
conversion process is timed by the SCK input clock. For
optimum performance, CNV should be driven by a clean
low jitter signal. The Typical Application at the back of the
data sheet illustrates a recommended implementation to
reduce the relatively large jitter from an FPGA CNV pulse
source. Note the low jitter input clock times the falling edge
of the CNV signal. The rising edge jitter of CNV is much
less critical to performance. The typical pulse width of the
CNV signal is 30ns at a 5Msps conversion rate.
SCK Serial Data Clock Input
The falling edge of this clock shifts the conversion result
MSB first onto the SDO pins. A 105MHz external clock must
be applied at the SCK pin to achieve 5Msps throughput.
CLKOUT Serial Data Clock Output
The CLKOUT output provides a skew-matched clock to
latch the SDO output at the receiver. The timing skew
of the CLKOUT and SDO outputs are matched. For high
throughput applications, using CLKOUT instead of SCK
to capture the SDO output eases timing requirements at
the receiver. For low throughput applications, CLKOUT⁺
can be disabled by tying CLKOUT^– to OV_DD.
Nap/Sleep Modes
Nap mode is a method to save power without sacrificing
power-up delays for subsequent conversions. Sleep mode
has substantial power savings, but a power-up delay is
incurred to allow the reference and power systems to
become valid. To enter nap mode on the LTC2323-12,
the SCK signal must be held high or low and a series of
two CNV pulses must be applied. This is the case for both
CMOS and LVDS modes. The second rising edge of CNV
initiates the nap state. The nap state will persist until either
a single rising edge of SCK is applied, or further CNV pulses
are applied. The SCK rising edge will put the LTC2323-12
back into the operational (full-power) state. When in nap
mode, two additional pulses will put the LTC2323-12 in
sleep mode. When configured for CMOS I/O operation, a
single rising edge of SCK can return the LTC2323-12 into
operational mode. A 10ms delay is necessary after exiting
sleep mode to allow the reference buffer to recharge the
external filter capacitor. In LVDS mode, exit sleep mode
by supplying a fifth CNV pulse. The fifth pulse will return
the LTC2323-12 to operational mode, and further SCK
pulses will keep the part from re-entering nap and sleep
modes. The fifth SCK pulse also works in CMOS mode
as a method to exit sleep. In the absence of SCK pulses,
repetitive CNV pulses will cycle the LTC2323-12 between
operational, nap and sleep modes indefinitely.
Refer to the timing diagrams in Figure 18, Figure 19, Figure 20
and Figure 21 for more detailed timing information about
sleep and nap modes.
CNV
SCK
SDO1
SDO2
1
2
NAP MODE
HOLD STATIC HIGH OR LOW
Z
Z
FULL POWER MODE
WAKE ON 1ST SCK EDGE
232312 F18
Figure 18. CMOS and LVDS Mode NAP and WAKE Using SCK
For more information www.linear.com/LTC2323-12
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