LTC2241-12 Datasheet, PDF (19/28 Pages) Linear Technology – 12-Bit, 210Msps ADC

APPLICATIO S I FOR ATIO
LTC2241-12
V_DD
CLOCK
INPUT
T1
MA/COM
0.1µF _ETC1-1-13
•
•
50Ω
0.1µF
50Ω
ENC⁺
8.2pF 100Ω
0.1µF
ENC–
V_DD ^{1.5V BIAS}
4.8k
V_DD ^{1.5V BIAS}
4.8k
Figure 11. Transformer Driven ENC⁺/ENC^–
LTC2241-12
TO INTERNAL
ADC CIRCUITS
224112 F11
V_THRESHOLD = 1.5V
ENC⁺
1.5V ENC^{– LTC2241-12}
0.1µF
224112 F12a
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
LVDS
CLOCK
0.1µF
ENC⁺
100Ω _0.1µF
LTC2241-12
ENC^–
224112 F12b
Figure 12b. ENC Drive Using LVDS
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2241-12 is 210Msps.
For the ADC to operate properly, the encode signal should
have a 50% (±5%) duty cycle. Each half cycle must have
at least 2.26ns for the ADC internal circuitry to have
enough settling time for proper operation. Achieving a
precise 50% duty cycle is easy with differential sinusoidal
drive using a transformer or using symmetric differential
logic such as PECL or LVDS.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the ENC⁺ pin to sample the analog
input. The falling edge of ENC⁺ is ignored and the internal
falling edge is generated by a phase-locked loop. The input
clock duty cycle can vary from 40% to 60% and the clock
duty cycle stabilizer will maintain a constant 50% internal
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require one
hundred clock cycles for the PLL to lock onto the input
clock. To use the clock duty cycle stabilizer, the MODE pin
should be connected to 1/3V_DD or 2/3V_DD using external
resistors.
The lower limit of the LTC2241-12 sample rate is deter-
mined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum operat-
ing frequency for the LTC2241-12 is 1Msps.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
224112fa
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