LT1763_1 Datasheet, PDF (19/20 Pages) Linear Technology – 500mA, Low Noise, LDO Micropower Regulators

PACKAGE DESCRIPTION
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695 Rev D)
LT1763 Series
0.70 p0.05
3.60 p0.05
2.20 p0.05
3.30 p0.05
1.70 p 0.05
PIN 1
TOP MARK
(NOTE 6)
PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
2.50 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.200 REF
4.00 p0.10
(2 SIDES)
R = 0.05
TYP
3.00 p0.10
(2 SIDES)
0.75 p0.05
0.00 – 0.05
R = 0.115
7
TYP
0.40 p 0.10
12
3.30 p0.10
1.70 p 0.10
6
0.25 p 0.05
2.50 REF
1
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH
R = 0.20 OR
0.35 s 45o
CHAMFER
(UE12/DE12) DFN 0806 REV D
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
5. EXPOSED PAD SHALL BE SOLDER PLATED
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
2. DRAWING NOT TO SCALE
ON THE TOP AND BOTTOM OF PACKAGE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.050 BSC
.045 ±.005
.189 – .197
(4.801 – 5.004)
NOTE 3
8
7
6
5
.053 – .069
(1.346 – 1.752)
.245
MIN
.160 ±.005 _{.228 – .244}
(5.791 – 6.197)
.150 – .157
(3.810 – 3.988)
NOTE 3
.014 – .019
(0.355 – 0.483)
TYP
.030 ±.005
TYP
RECOMMENDED SOLDER PAD LAYOUT
1
2
34
NOTE:
1. DIMENSIONS
IN
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
.010 – .020 _{s 45°}
(0.254 – 0.508)
.008 – .010
(0.203 – 0.254)
.016 – .050
(0.406 – 1.270)
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
0°– 8° TYP
SO8 0303
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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