LTC2401_15 Datasheet, PDF (18/32 Pages) Linear Technology – 1-/2-Channel 24-Bit Power No Latency ADCs in MSOP-10

LTC2401/LTC2402
APPLICATIO S I FOR ATIO
CS
SDO
Hi-Z
<t_EOCtest
2.7V TO 5.5V
1µF
REFERENCE VOLTAGE
ZS_SET + 0.1V TO V_CC
ANALOG INPUT RANGE
ZS_SET – 0.12V_REF TO
FS_SET + 0.12V_REF
(V_REF = FS_SET – ZS_SET)
0V TO FS_SET – 100mV
1
V_CC
10
F_O
LTC2402
2
FS_SET
9
SCK
3
CH1
SDO ⁸
4
CH0
CS ⁷
5
6
ZS_SET GND
TEST EOC
Hi-Z
BIT 31 BIT 30
EOC CH0/CH1
BIT 29
SIG
BIT 28
EXR
BIT 27
MSB
BIT 26
V_CC
V_CC
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
10k
= INTERNAL OSC/60Hz REJECTION
BIT 4
LSB₂₄
BIT 0
TEST EOC
Hi-Z
Hi-Z
SCK
(INTERNAL)
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
2400 F08
Figure 8. Internal Serial Clock, Single Cycle Operation
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t_EOCtest after the falling edge of CS
(if EOC = 0) or t_EOCtest after EOC goes LOW (if CS is LOW
during the falling edge of EOC). The value of t_EOCtest is 23µs
if the device is using its internal oscillator (F₀ = logic LOW
or HIGH). If F_O is driven by an external oscillator of
frequency f_EOSC, then t_EOCtest is 3.6/f_EOSC. If CS is pulled
HIGH before time t_EOCtest, the device remains in the sleep
state. The conversion result is held in the internal static
shift register.
If CS remains LOW longer than t_EOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH, and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 9. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
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