LTC2282 Datasheet, PDF (18/24 Pages) Linear Technology – Dual 12-Bit, 105Msps Low Power 3V ADC

LTC2282
APPLICATIONS INFORMATION
Table 2. MODE Pin Function
MODE Pin
0
1/3V_DD
2/3V_DD
V_DD
Output Format
Offset Binary
Offset Binary
2’s Complement
2’s Complement
Clock Duty
Cycle Stabilizer
Off
On
On
Off
Overflow Bit
When OF outputs a logic high the converter is either over-
ranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV_DD, should be tied to the
same power supply as for the logic being driven. For example,
if the converter is driving a DSP powered by a 1.8V supply,
then OV_DD should be tied to that same 1.8V supply.
OV_DD can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND
up to 1V and must be less than OV_DD. The logic outputs
will swing between OGND and OV_DD.
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF. The
data access and bus relinquish times are too slow to
allow the outputs to be enabled and disabled during full
speed operation. The output Hi-Z state is intended for use
during long periods of inactivity. Channels A and B have
independent output enable pins (OEA, OEB).
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to V_DD and OE to V_DD
results in sleep mode, which powers down all circuitry,
including the reference, and typically dissipates 1mW.
When exiting sleep mode, it will take milliseconds for the
output data to become valid because the reference capaci-
tors have to recharge and stabilize. Connecting SHDN to
V_DD and OE to GND results in nap mode, which typically
dissipates 30mW. In nap mode, the on-chip reference circuit
is kept on, so that recovery from nap mode is faster than
that from sleep mode, typically taking 100 clock cycles. In
both sleep and nap modes, all digital outputs are disabled
and enter the Hi-Z state.
Channels A and B have independent SHDN pins (SHDNA,
SHDNB). Channel A is controlled by SHDNA and OEA, and
channel B is controlled by SHDNB and OEB. The nap, sleep
and output enable modes of the two channels are completely
independent, so it is possible to have one channel operating
while the other channel is in nap or sleep mode.
Digital Output Multiplexer
The digital outputs of the LTC2282 can be multiplexed onto
a single data bus if the sample rate is 80Msps, or less. The
MUX pin is a digital input that swaps the two data busses.
If MUX is high, channel A comes out on DA0-DA11, OFA;
channel B comes out on DB0-DB11, OFB. If MUX is low,
the output busses are swapped and channel A comes out
on DB0-DB11, OFB; channel B comes out on DA0-DA11,
OFA. To multiplex both channels onto a single output bus,
connect MUX, CLKA and CLKB together (see the Timing
Diagram for the multiplexed mode). The multiplexed data
is available on either data bus—the unused data bus can
be disabled with its OE pin.
Grounding and Bypassing
The LTC2282 requires a printed circuit board with a clean,
unbroken ground plane. A multilayer board with an internal
ground plane is recommended. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC.
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