LTC2171-12_15 Datasheet, PDF (18/34 Pages) Linear Technology – 12-Bit, 65Msps/40Msps/ 25Msps Low Power Quad ADCs

LTC2172-12/
LTC2171-12/LTC2170-12
Pin Functions
PAR/SER (Pin 47): Programming Mode Selection Pin.
Connect to ground to enable serial programming mode.
CS, SCK, SDI and SDO become a serial interface that con-
trols the A/D operating modes. Connect to V_DD to enable
parallel programming mode where CS, SCK, SDI and SDO
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or the V_DD of the part and not be driven
by a logic signal.
V_REF (Pin 48): Reference Voltage Output. Bypass to ground
with a 1µF ceramic capacitor, nominally 1.25V.
SENSE (Pin 50): Reference Programming Pin. Connect-
ing SENSE to V_DD selects the internal reference and a
±1V input range. Connecting SENSE to ground selects
the internal reference and a ±0.5V input range. An external
reference between 0.625V and 1.3V applied to SENSE
selects an input range of ±0.8 • V_SENSE.
LVDS Outputs
The following pins are differential LVDS outputs. The
output current level is programmable. There is an op-
tional internal 100Ω termination resistor between the
pins of each LVDS output pair.
OUT4B^–/OUT4B⁺, OUT4A^–/OUT4A⁺ (Pins 23/24,
Pins 25/ 26): Serial Data Outputs for Channel 4. In 1-lane
output mode, only OUT4A^–/OUT4A⁺ are used.
OUT3B^–/OUT3B⁺, OUT3A^–/OUT3A⁺ (Pins 27/28,
Pins 29/30): Serial Data Outputs for Channel 3. In
1-lane output mode, only OUT3A^–/OUT3A⁺ are used.
FR^–/FR⁺ (Pin 31/Pin 32): Frame Start Output.
DCO^–/DCO⁺ (Pin 35/Pin 36): Data Clock Output.
OUT2B^–/OUT2B⁺, OUT2A^–/OUT2A⁺ (Pins 37/38,
Pins 39/40): Serial Data Outputs for Channel 2. In
1-lane output mode, only OUT2A^–/OUT2A⁺ are used.
OUT1B^–/OUT1B⁺, OUT1A^–/OUT1A⁺ (Pins 41/42,
Pins 43/44): Serial Data Outputs for Channel 1. In
1-lane output mode, only OUT1A^–/OUT1A⁺ are used.
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