LTC1538-AUX_15 Datasheet, PDF (18/32 Pages) Linear Technology – Dual High Efficiency, Low Noise, Synchronous Step-Down Switching Regulators

LTC1538-AUX/LTC1539
APPLICATIONS INFORMATION
1.3
f_O
0.7
0
0.5
1.0
1.5
2.0
2.5
V_PLLLPF (V)
1538 F07
Figure 7. Operating Frequency vs V_PLLLPF
EXTERNAL
FREQUENCY
2.4V
PHASE
DETECTOR*
*PLLIN
SGND
50k
DIGITAL
PHASE/
FREQUENCY
DETECTOR
R_LP
C_LP
C_OSC
*PLL LPF
C_OSC
OSC
*LTC1539 ONLY
1538 F08
Figure 8. Phase-Locked Loop Block Diagram
Phase-Locked Loop and Frequency Synchronization
The LTC1539 has an internal voltage-controlled oscillator
and phase detector comprising a phase-locked loop. This
allows the top MOSFET turn-on to be locked to the rising
edge of an external source. The frequency range of the
voltage-controlled oscillator is ±30% around the center
frequency f_O.
The value of C_OSC is calculated from the desired operating
frequency (f_O). Assuming the phase-locked loop is locked
(V_PLLLPF = 1.19V):
( ) ^{2.1 104}
C _OSC
(pF)
=
Frequency
–
(kHz)
11
Stating the frequency as a function of V_PLLLPF and C_OSC:
Frequency(kHz) =
( ) ^{8.4 108}


[ ] ^COSC^(pF)
+ 11


^{17 µA}
1
+
18µA^{}
V_PLLLPF
2.4V

+

2000^


The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, ∆f_H, is equal to the capture range, ∆f_C:
∆f_H = ∆f_C = ±0.3 f_O.
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLL LPF pin. A simplified block
diagram is shown in Figure 8.
If the external frequency f_PLLIN is greater than the oscilla-
tor frequency f_OSC, current is sourced continuously, pull-
ing up the PLL LPF pin. When the external frequency is less
than f_0SC, current is sunk continuously, pulling down the
PLL LPF pin. If the external and internal frequencies are the
same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. Thus the voltage on the PLL LPF pin is adjusted
until the phase and frequency of the external and internal
oscillators are identical. At this stable operating point the
phase comparator output is open and the filter capacitor
C_LP holds the voltage. The LTC1539 PLLIN pin must be
driven from a low impedance such as a logic gate located
close to the pin. Any external attenuator used needs to be
referenced to SGND.
The loop filter components C_LP, R_LP smooth out the
current pulses from the phase detector and provide a
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