LTC1408-12_15 Datasheet, PDF (18/20 Pages) Linear Technology – 6 Channel, 12-Bit, 600ksps Simultaneous Sampling ADC with Shutdown

LTC1408-12
APPLICATIO S I FOR ATIO
High quality tantalum and ceramic bypass capacitors should
be used at the V_CC, V_DD and V_REF pins as shown in the
Block Diagram on the first page of this data sheet. For
optimum performance, a 10µF surface mount tantalum
capacitor with a 0.1µF ceramic is recommended for the
V_CC, V_DD and V_REF pins. Alternatively, 10µF ceramic chip
capacitors such as X5R or X7R may be used. The capaci-
tors must be located as close to the pins as possible. The
traces connecting the pins and the bypass capacitors must
be kept short and should be made as wide as possible. The
V_CC and V_DD bypass capacitor returns to the ground plane
and the V_REF bypass capacitor returns to the Pin 22. Care
should be taken to place the 0.1µF V_CC and V_DD bypass
capacitor as close to Pins 24 and 25 as possible.
Figure 6 shows the recommended system ground connec-
tions. All analog circuitry grounds should be terminated at
the LTC1408-12 Exposed Pad. The ground return from the
LTC1408-12 to the power supply should be low imped-
ance for noise-free operation. The Exposed Pad of the 32-
pin QFN package is also internally tied to the ground pads.
The Exposed Pad should be soldered on the PC board to
reduce ground connection inductance. All ground pins
(GND, DGND, OGND) must be connected directly to the
same ground plane under the LTC1408-12.
HARDWARE INTERFACE TO TMS320C54x
The LTC1408-12 is a serial output ADC whose interface
has been designed for high speed buffered serial ports in
fast digital signal processors (DSPs). Figure 7 shows an
example of this interface using a TMS320C54X.
The buffered serial port in the TMS320C54x has direct
access to a 2kB segment of memory. The ADC’s serial
data can be collected in two alternating 1kB segments, in
real time, at the full 600ksps conversion rate of the
LTC1408-12. The DSP assembly code sets frame sync
mode at the BFSR pin to accept an external positive going
pulse and the serial clock at the BCLKR pin to accept an
external positive edge clock. Buffers near the LTC1408-12
may be added to drive long tracks to the DSP to prevent
corruption of the signal to LTC1408-12. This configura-
tion is adequate to traverse a typical system board, but
source resistors at the buffer outputs and termination
resistors at the DSP, may be needed to match the charac-
teristic impedance of very long transmission lines. If you
need to terminate the SDO transmission line, buffer it first
with one or two 74ACxx gates. The TTL threshold inputs of
the DSP port respond properly to the 3V swing used with
the LTC1408-12.
OV_DD BYPASS,
0.1µF, 0402
V_DD BYPASS,
0.1µF, 0402
V_CC BYPASS,
0.1µF, 0402 AND
10µF, 0805
V_REF BYPASS,
10µF, 0805
Figure 6. Recommended Layout
LTC1408-12
3V
3
OV_DD
30
CONV
32
SCK
1
SDO
2
OGND
DGND ³¹
CONV
CLK
3-WIRE SERIAL
INTERFACE LINK
0V TO 3V LOGIC SWING
5V
TMS320C54x
V_CC
BFSR
B11 B10
BCLKR
BDR
1408 F06
Figure 7. DSP Serial Interface to TMS320C54x
140812f
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