LT3437 Datasheet, PDF (18/24 Pages) Linear Technology – High Voltage 500mA, 200kHz Step-Down Switching Regulator with 100uA Quiescent Current

LT3437
APPLICATIO S I FOR ATIO
inductance of approximately 25nH/inch. At switch off, this
parasitic inductance produces a flyback spike across the
LT3437 switch. When operating at higher currents and
input voltages, with poor layout, this spike can generate
voltages across the LT3437 that may exceed its absolute
maximum rating. A ground plane should always be used
under the switcher circuitry to prevent interplane coupling
and overall noise.
LT3437
V_IN
SW
+ ^VIN
HIGH
C2 FREQUENCY
CIRCULATION
PATH
L1
V_OUT
D1
C1 LOAD
3437 F08
Figure 8. High Speed Switching Path
The V_C and FB components should be kept as far away as
possible from the switch and boost nodes. The LT3437
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic oscillation.
Board layout also has a significant effect on thermal
resistance. Pin 4/Pin 10 and the exposed die pad, Pin 11/
Pin 17, are connected by a continuous copper plate that
runs under the LT3437 die. This is the best thermal path
for heat out of the package. Reducing the thermal resis-
tance from Pin 4 and the exposed pad onto the board will
reduce die temperature and increase the power capability
of the LT3437. This is achieved by providing as much
copper area as possible around the exposed pad. Adding
multiple solder filled feedthroughs, under and around this
pad, to an internal ground plane will also help. Similar
treatment to the catch diode and coil terminations will
reduce any additional heating effects.
L1
C1 ^D1
C2
FE PACKAGE TOPSIDE METAL
3437 F09a
C1
D1
L1
C2
18
DD PACKAGE TOPSIDE METAL
3437 F09b
Figure 9. Suggested Layouts
THERMAL CALCULATIONS
Power dissipation in the LT3437 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following formu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, and should
not be used for calculating efficiency at light load currents.
Switch loss:
( ) ( ) _{( )( )( )( )} ²
R_SW I_OUT V_OUT
P_SW =
V_IN
+ t_EFF 1/2 I_OUT V_IN f
Boost current loss:
( ) ( ) _{PBOOST =}
V_OUT
2 _IOUT/30
V_IN
Quiescent current loss:
P_Q = V_IN (500µA) + V_OUT (800µA)
R_SW = switch resistance (≈1 when hot )
t_EFF = effective switch current/voltage overlap time
3437f