LT1976B_15 Datasheet, PDF (18/28 Pages) Linear Technology – High Voltage 1.5A, 200kHz Step-Down Switching Regulator with 100A Quiescent Current

LT1976/LT1976B
APPLICATIO S I FOR ATIO
V_OUT
0.5V/DIV
C_SS = GND
C_SS = 0.1μF
C_SS = 0.1μF
C_OUT = 47μF
I_LOAD = 200mA
V_IN = 12V
TIME (1ms/DIV)
Figure 4. V_OUT dV/dt
1976 F04
Burst Mode OPERATION (LT1976 ONLY)
To enhance efficiency at light loads, the LT1976 automati-
cally switches to Burst Mode operation which keeps the
output capacitor charged to the proper voltage while mini-
mizing the input quiescent current. During Burst Mode
operation, the LT1976 delivers short bursts of current to
the output capacitor followed by sleep periods where the
output power is delivered to the load by the output capaci-
tor. In addition, V_IN and BIAS quiescent currents are re-
duced to typically 45μA and 125μA respectively during the
sleep time. As the load current decreases towards a no
load condition, the percentage of time that the LT1976
operates in sleep mode increases and the average input
current is greatly reduced resulting in higher efficiency.
The minimum average input current depends on the V_IN to
V_OUT ratio, V_C frequency compensation, feedback divider
network and Schottky diode leakage. It can be approxi-
mated by the following equation:
( _{( )} ) _IIN(AVG)
≅
I_VINS
+
I_SHDN
+
⎛
⎝⎜
V_OUT
V_IN
⎞
⎠⎟
I_BIASS + I_FB + I_S
η
where
I_VINS = input pin current in sleep mode
V_OUT = output voltage
V_IN = input voltage
I_BIASS = BIAS pin current in sleep mode
I_FB = feedback network current
I_S = catch diode reverse leakage at V_OUT
η = low current efficiency (non Burst Mode operation)
18
Example: For V_OUT = 3.3V, V_IN = 12V
I_IN(AVG)
=
45μA
+
5μA
+
⎛
⎝⎜
3.3⎞
12 ⎠⎟
(125μA
+
12.5μA
(0.8)
+
0.5μA)
= 45μA + 5μA + 47μA = 97μA
During the sleep portion of the Burst Mode cycle, the V_C
pin voltage is held just below the level needed for normal
operation to improve transient response. See the Typical
Performance Characteristics section for burst and tran-
sient response waveforms.
If a no load condition can be anticipated, the supply current
can be further reduced by cycling the SHDN pin at a rate
higher than the natural no load burst frequency. Figure 6
shows Burst Mode operation with the SHDN pin. V_OUT
burst ripple is maintained while the average supply current
150
V_OUT = 3.3V
T_A = 25°C
125
100
75
50
25
0
0 10 20 30 40 50 60
INPUT VOLTAGE (V)
1976 F05
Figure 5. I_Q vs V_IN
V_OUT
50mV/DIV
V_SHDN
2V/DIV
I_SW
500mA/DIV
V_IN = 12V
V_OUT = 3.3V
I_Q = 15μA
TIME (50ms/DIV)
1976 G16
Figure 6. Burst Mode with Shutdown Pin
1976bfg