LT1507 Datasheet, PDF (18/20 Pages) Linear Technology – 500kHz Monolithic Buck Mode Switching Regulator

LT1507
APPLICATIONS INFORMATION
Example: with V_IN = 5V, V_OUT = 3.3V, I_OUT = 1A;
( ) ( ) ^PSW
=
(0.4)(1)²(3.3) ₊
5
₁₆
10^−9
₍₁₎₍₅₎₅₀₀
10³


= 0.26 + 0.04 = 0.3W
P_BOOST
=
(3.3)²
5
_0.008
+
1
75 _
=
0.046W
P_Q = 5(0.003) + 3.3(0.005) = 0.032W
Total power dissipation is 0.3 + 0.046 + 0.032 = 0.38W.
Thermal resistance for the LT1507 packages is influenced
by the presence of internal or backside planes. With a full
plane under the SO package, thermal resistance will be
about 120°C/W. No plane will increase resistance to about
150°C/W. To calculate die temperature, use the proper
thermal resistance number for the desired package and
add in worst-case ambient temperature;
T_J = T_A + θ_JA(P_TOT)
With the S8 package (θ_JA = 120°C/W) at an ambient
temperature of 70°C;
T_J = 70 + 120(0.38) = 116°C
FREQUENCY COMPENSATION
The LT1507 uses a “current mode” architecture to help
alleviate phase shift created by the inductor. The basic
connections are shown in Figure 9. Gain of the power stage
can be modeled as 1.8A/V transconductance from the V_C
pin voltage to current delivered to the output. This is
shown in Figure 8 where the transconductance from V_C
pin to inductor current is essentially flat from 50Hz to
50kHz and phase shift is minimal in the important loop
unity-gain band of 1kHz to 50kHz. Inductor variation from
3µH to 20µH will have very little effect on these curves.
Overall gain from the V_C pin to output is then modeled as
the product of 1.8A/ V transconductance multiplied by the
complex impedance of the load in parallel with the output
capacitor model.
The error amplifier can be modeled as a transconductance
of 2000µmho, with an output impedance of 200kΩ in
2.0
80
GAIN (A/V)
1.5
40
1.0
0
PHASE
0.5 VOUT = 3.3V
I_OUT = 250mA
V_IN = 5V
L = 10µH
0
10
100
1k
10k
FREQUENCY (Hz)
–40
–80
100k
LT1507 • F08
Figure 8. Phase and Gain from V_C Pin Voltage
to Inductor Current
parallel with 12pF. In all practical applications, the com-
pensation network from V_C pin to ground has a much
lower impedance than the output impedance of the ampli-
fier at frequencies above 500Hz. This means that the error
amplifier characteristics themselves do not contribute
excess phase shift to the loop and the phase/gain charac-
teristics of the error amplifier section are completely
controlled by the external compensation network.
The complete small-signal model is shown in Figure 9. R1
and R2 are the divider used to set output voltage. These are
internal on the fixed voltage LT1507-3.3 with R1 = 1.8k
and R2 = 5k. R_C, C_C and C_F are external compensation
POWER STAGE
g_m = 1.8A/V
LT1507
12pF
ERROR AMPLIFIER
g_m = 2000µho
200k
V_{SW L1}
F_B
2.42V
GND
V_C
R_C
C_F
C_C
OUTPUT
R1
ESR
C1
R2
1507 • F09
Figure 9. Small-Signal Model for Loop Stability Analysis
18