LTC3550-1_15 Datasheet, PDF (17/24 Pages) Linear Technology – Dual Input USB/AC Adapter Li-Ion Battery Charger with 600mA Buck Converter

LTC3550-1
APPLICATIO S I FOR ATIO
Using Ceramic Input and Output Capacitors
Higher capacitance values, lower cost ceramic capacitors
are now becoming available in smaller case sizes. Their
high ripple current, high voltage rating and low ESR make
them ideal for switching regulator applications. Because the
LTC3550-1’s control loop does not depend on the output
capacitor’s ESR for stable operation, ceramic capacitors
can be used freely to achieve very low output ripple and
small circuit size.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses in LTC3550-1 circuits: V_CC quiescent current
and I²R losses. The V_CC quiescent current loss dominates
the efficiency loss at very low load currents whereas the
I²R loss dominates the efficiency loss at medium to high
load currents. In a typical efficiency plot, the efficiency
curve at very low load currents can be misleading since
the actual power lost is of no consequence as illustrated
in Figure 3.
1. The V_CC quiescent current is due to two components:
the DC bias current as given in the Electrical Charac-
teristics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate
is switched from high to low to high again, a packet of
charge, dQ, moves from V_CC to ground. The resulting
dQ/dt is the current out of V_CC that is typically larger
than the DC bias current. In continuous mode, I_GATECHG
= f(Q_T + Q_B) where Q_T and Q_B are the gate charges of
the internal top and bottom switches. Both the DC bias
and gate charge losses are proportional to V_CC and
thus their effects will be more pronounced at higher
supply voltages.
2. I²R losses are calculated from the resistances of the
internal switches, R_SW, and external inductor R_L. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R_DS(ON) and the duty cycle
(DC) as follows:
R_SW = (R_DS(ON)TOP)(DC) + (R_DS(ON)BOT)(1 – DC)
The R_DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I²R losses, simply add R_SW to R_L
and multiply the result by the square of the average output
current. Other losses including C_IN and C_OUT ESR dissipa-
tive losses and inductor core losses generally account for
less than 2% total additional loss.
1
0.1
0.01
0.001
0.0001
0.00001
0.1
1
10
100
LOAD CURRENT (mA)
1000
3550-1 F03
Figure 3. Power Lost vs Load Current
35501f
17