LTC2499_1 Datasheet, PDF (17/34 Pages) Linear Technology – 24-Bit 8-/16-Channel ΔΣ ADC with Easy Drive Input Current Cancellation and I2C Interface

LTC2499
APPLICATIONS INFORMATION
INPUT DATA FORMAT
The serial input word to the LTC2499 is 13 bits long and
is written into the device input register in two 8-bit words.
The first word (SGL, ODD, A2, A1, A0) is used to select
the input channel. The second word of data (IM, FA, FB,
SPD) is used to select the frequency rejection, speed mode
(1x, 2x), and temperature measurement.
After power-up, the device initiates an internal reset cycle
which sets the input channel to CH0-CH1 (IN⁺ = CH0, IN^– =
CH1), the frequency rejection to simultaneous 50Hz/60Hz,
and 1x output rate (auto-calibration enabled). The first
conversion automatically begins at power-up using this
default configuration. Once the conversion is complete,
up to two words may be written into the device.
The first three bits of the first input word consist of two
preamble bits and one enable bit. Valid settings for these
three bits are 000, 100, and 101. Other combinations
should be avoided.
If the first three bits are 000 or 100, the following data
is ignored (don’t care) and the previously selected input
channel remains valid for the next conversion
If the first three bits shifted into the device are 101, then
the next five bits select the input channel for the next
conversion cycle (see Table 3).
The first input bit (SGL) following the 101 sequence de-
termines if the input selection is differential (SGL = 0) or
single-ended (SGL = 1). For SGL = 0, two adjacent chan-
nels can be selected to form a differential input. For SGL
= 1, one of 16 channels is selected as the positive input.
The negative input is COM for all single-ended operations.
The remaining four bits (ODD, A2, A1, A0) determine
which channel(s) is/are selected and the polarity (for a
differential input).
Once the first word is written into the device, a second
word may be input in order to select a configuration mode.
1… 7
8
9
1
2…
9
1
2
3
4
5
6
7
89
START BY
MASTER
7-BIT
ADDRESS
R
SGN
ACK BY
LTC2499
SLEEP
MSB DIS
ACK BY
MASTER
LSB
DATA OUTPUT
SUB LSBs
Figure 3a. Timing Diagram for Reading from the LTC2499
NAK BY
MASTER
2499 F03a
SCL
1 2… 7 8 9
1 2 3 4 5 6 7 89
1 2 3 4 5 6 7 89
SDA
START BY
MASTER
7-BIT ADDRESS W
1 0 EN SGL ODD A2 A1 A0
EN2 IM FA FB SPD
SLEEP
ACK BY
LTC2499
ACK
LTC2499
DATA INPUT
(OPTIONAL 2ND BYTE)
Figure 3b. Timing Diagram for Writing to the LTC2499
ACK
LTC2499
2499 F03b
2499fc
17