LTC2436-1_15 Datasheet, PDF (17/28 Pages) Linear Technology – 2-Channel Differential Input 16-Bit No Latency ADC

LTC2436-1
APPLICATIO S I FOR ATIO
2.7V TO 5.5V
V_CC
1µF
REFERENCE
VOLTAGE
0.1V TO V_CC
1
V_CC
14
F_O
LTC2436-1
2 _REF+
3 _REF–
13
SCK
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
10k
ANALOG INPUT RANGE
–0.5V_REF TO 0.5V_REF
4 _CH0+
5 _CH0–
6 _CH1+
12
SDO
11
CS
3-WIRE
SPI INTERFACE
7 _CH1–
8, 9, 10, 15, 16
GND
> t_EOCtest
<t_EOCtest
CS
SDO
Hi-Z
BIT 0
EOC
TEST EOC
Hi-Z
Hi-Z
BIT 18
EOC
Hi-Z
BIT 17
CH0/CH1
BIT 16
SIG
BIT 15
MSB
BIT 14
BIT 13
BIT 2
TEST EOC
Hi-Z
SCK
(INTERNAL)
SLEEP
DATA
OUTPUT
CONVERSION
SLEEP SLEEP
TEST EOC
(OPTIONAL)
DATA OUTPUT
Figure 10. Internal Serial Clock, Reduced Data Output Length
CONVERSION
24361 F10
disabled. Hence, SCK remains LOW. On the next falling
edge of CS, the device is switched to the external SCK
timing mode. By adding an external 10k pull-up resistor to
SCK, this pin goes HIGH once the external driver goes
Hi-Z. On the next CS falling edge, the device will remain in
the internal SCK timing mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the
conversion status. If the device is in the sleep state (EOC
= 0), SCK will go LOW. Once CS goes HIGH (within the time
period defined above as t_EOCtest), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 11. CS may be permanently tied to ground, simpli-
fying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after V_CC exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
24361f
17