LTC2305_15 Datasheet, PDF (17/26 Pages) Linear Technology – 1-/2-Channel, 12-Bit ADCs with I2C Compatible Interface

LTC2301/LTC2305
APPLICATIONS INFORMATION
Output Data Format
The output register contains the last conversion result.
After each conversion is completed, the device automati-
cally enters either nap or sleep mode depending on the
setting of the SLP bit (see Nap Mode and Sleep Mode
sections). When the LTC2301/LTC2305 is addressed for a
read operation, it acknowledges by pulling SDA LOW and
acts as a transmitter. The master/receiver can read up to
two bytes from the LTC2301/LTC2305. After a complete
read operation of 2 bytes, a STOP condition is needed to
initiate a new conversion. The device will NACK subsequent
read operations while a conversion is being performed.
The data output stream is 16 bits long and is shifted out
on the falling edges of SCL (see Figure 7a). The first bit
is the MSB and the 12th bit is the LSB of the conversion
result. The remaining four bits are zero. Figures 13 and 14
are the transfer characteristics for the bipolar and unipolar
modes. Data is output on the SDA line in 2’s complement
format for bipolar readings and in straight binary for
unipolar readings.
Input Data Format
When the LTC2301/LTC2305 is addressed for a write op-
eration, it acknowledges by pulling SDA LOW during the
LOW period before the 9th cycle and acts as a receiver.
The master/transmitter can then send 1 byte to program
the device. The input byte consists of the 6-bit D_IN word
followed by two bits that are ignored by the ADC and are
considered don’t cares (X) (see Figure 7b). The input bits
are latched on the rising edge of SCL during the write
operation.
123456789
123456789
SCL
•••
SDA
START BY
MASTER
A6 A5 A4 A3 A2 A1 A0 R/W
B11 B10 B9 B8 B7 B6 B5 B4
•••
ADDRESS FRAME
ACK BY
ADC
MOST SIGNIFICANT DATA BYTE
READ 1 BYTE
ACK BY
MASTER
SCL
(CONTINUED)
•••
SDA
(CONTINUED)
•••
123456789
B3 B2 B1 B0
LEAST SIGNIFICANT DATA BYTE
READ 1 BYTE
CONVERSION
INITIATED
NACK BY
MASTER
STOP
BY MASTER
23015 F07a
Figure 7a. Timing Diagram for Reading from the LTC2301/LTC2305
NOTE: S/D BIT IS A DON’T CARE (X) FOR THE LTC2301
123456789
SCL
SDA
START BY
MASTER
A6 A5 A4 A3 A2 A1 A0 R/W
ADDRESS FRAME
ACK BY
ADC
123456789
CONVERSION
INITIATED
S/D O/S X X UNI SLP X X
STOP BY
D_IN WORD
ACK BY ^MASTER
ADC
WRITE 1 BYTE
23015 F07b
Figure 7b. Timing Diagram for Writing to the LTC2301/LTC2305
23015fb
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