LTC2252_15 Datasheet, PDF (17/24 Pages) Linear Technology – 12-Bit, 125/105Msps Low Power 3V ADCs

LTC2253/LTC2252
APPLICATIO S I FOR ATIO
a transformer provides no incremental contribution to
phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz
will degrade the SNR compared to the transformer solu-
tion. The nature of the received signals also has a large
bearing on how much SNR degradation will be experi-
enced. For high crest factor signals such as WCDMA or
OFDM, where the nominal power level must be at least 6dB
to 8dB below full scale, the use of these translators will
have a lesser impact.
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may be
desirable in cases where lower voltage differential signals
are considered. The center tap may be bypassed to ground
through a capacitor close to the ADC if the differential
signals originate on a different plane. The use of a capaci-
tor at the input may result in peaking, and depending on
transmission line length may require a 10Ω to 20Ω ohm
series resistor to act as both a low pass filter for high
frequency noise that may be induced into the clock line by
neighboring digital signals, as well as a damping mecha-
nism for reflections.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2253/LTC2252
is 125Msps (LTC2253) and 105Msps (LTC2252). The
lower limit of the LTC2253/LTC2252 sample rate is deter-
mined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum operat-
ing frequency for the LTC2253/LTC2252 is 1Msps.
Clock Duty Cycle Stabilizer
An optional clock duty cycle stabilizer circuit ensures
high performance even if the input clock has a non 50%
duty cycle. Using the clock duty cycle stabilizer is
recommended for most applications. To use the clock
duty cycle stabilizer, the MODE pin should be connected to
1/3V_DD or 2/3V_DD using external resistors.
This circuit uses the rising edge of the CLK pin to sample
the analog input. The falling edge of CLK is ignored and the
internal falling edge is generated by a phase-locked loop.
The input clock duty cycle can vary from 40% to 60% and
the clock duty cycle stabilizer will maintain a constant 50%
internal duty cycle. If the clock is turned off for a long
period of time, the duty cycle stabilizer circuit will require
a hundred clock cycles for the PLL to lock onto the
input clock.
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken
to make the sampling clock have a 50% (±5%) duty cycle.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits and the overflow bit.
Table 1. Output Codes vs Input Voltage
A_IN+ – A_IN–
(2V Range)
D11 – D0
OF (Offset Binary)
>+1.000000V
+0.999512V
+0.999024V
1 1111 1111 1111
0 1111 1111 1111
0 1111 1111 1110
+0.000488V
0.000000V
–0.000488V
–0.000976V
0 1000 0000 0001
0 1000 0000 0000
0 0111 1111 1111
0 0111 1111 1110
–0.999512V
–1.000000V
<–1.000000V
0 0000 0000 0001
0 0000 0000 0000
1 0000 0000 0000
D11 – D0
(2’s Complement)
0111 1111 1111
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
1000 0000 0000
Digital Output Buffers
Figure 14 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV_DD and OGND,
isolated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series
with the output makes the output appear as 50Ω to
external circuitry and may eliminate the need for external
damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2253/LTC2252 should drive a
minimal capacitive load to avoid possible interaction be-
tween the digital outputs and sensitive input circuitry. For
22532fa
17