LTC1966_11 Datasheet, PDF (17/38 Pages) Linear Technology – Precision Micropower RMS-to-DC Converter

Applications Information
120
C_AVE = 1µF
100
80
60
40
20
0
0
0.1
0.2
0.3
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0.5
TIME (SEC)
1966 F11a
Figure 11a. LTC1966 Rising Edge with C_AVE = 1µF
10
LTC1966
120
C_AVE = 1µF
100
80
60
40
20
0
0
0.2
0.4
0.6
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1
TIME (SEC)
1966 F11b
Figure 11b. LTC1966 Falling Edge with C_AVE = 1µF
C = 0.1µF C = 0.22µF C = 0.47µF
C = 1µF C = 2.2µF C = 4.7µF C = 10µF
C = 22µF C = 47µF C = 100µF
1
0.1
0.01
0.1
1
10
SETTLING TIME (SEC)
Figure 12. LTC1966 Settling Time with One Cap Averaging
100
1966 F12
decay type settling, they are not. This is due to the nonlinear
nature of an RMS-to-DC calculation. Also note the change
in the time scale between the two; the rising edge is more
than twice as fast to settle to a given accuracy. Again this
is a necessary consequence of RMS-to-DC calculation.^2 
Although shown with a step change between 0mV and
100mV, the same response shapes will occur with the
LTC1966 for ANY step size. This is in marked contrast
to prior generation log/antilog RMS-to-DC converters,
whose averaging time constants are dependent on the
signal level, resulting in excruciatingly long waits for the
output to go to zero.
The shape of the rising and falling edges will be dependent
on the total percent change in the step, but for less than
the 100% changes shown in Figure 11, the responses will
be less distorted and more like a standard exponential
decay. For example, when the input amplitude is changed
from 100mV to 110mV (+10%) and back (–10%), the step
responses are essentially the same as a standard expo-
nential rise and decay between those two levels. In such
cases, the time constant of the decay will be in between
that of the rising edge and falling edge cases of Figure 11.
Therefore, the worst case is the falling edge response as
it goes to zero, and it can be used as a design guide.
Figure 12 shows the settling accuracy vs settling time for
a variety of averaging capacitor values. If the capacitor
value previously selected (based on error requirements)
gives an acceptable settling time, your design is done.
2_{To convince oneself of this necessity, consider a pulse train of 50% duty cycle between 0mV}
and 100mV. At very low frequencies, the LTC1966 will essentially track the input. But as the input
frequency is increased, the average result will converge to the RMS value of the input. If the rise
and fall characteristics were symmetrical, the output would converge to 50mV. In fact though, the
RMS value of a 100mV DC-coupled 50% duty cycle pulse train is 70.71mV, which the asymmetrical
rise and fall characteristics will converge to as the input frequency is increased.
1966fb
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