LTM8055_15 Datasheet, PDF (16/24 Pages) Linear Technology – 36VIN, 8.5A Buck-Boost Module Regulator

LTM8055
Applications Information
2. Place the C_IN capacitor as close as possible to the V_IN
and GND connection of the LTM8055.
3. Place the C_OUT capacitor as close as possible to the
V_OUT and GND connection of the LTM8055.
4. Minimize the trace resistance between the optional
output current sense resistor, R_OUT, and V_OUT. Minimize
the loop area of the I_OUT trace and the trace from V_OUT
to R_OUT.
5. Minimize the trace resistance between the optional input
current sense resistor, R_IN and V_IN. Minimize the loop
area of the I_IN trace and the trace from V_IN to R_IN.
6. Place the C_IN and C_OUT capacitors such that their
ground current flow directly adjacent or underneath
the LTM8055.
7. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8055.
8. Use vias to connect the GND copper area to the board’s
internal ground planes. Liberally distribute these GND
vias to provide both a good ground connection and
thermal path to the internal planes of the printed circuit
board. Pay attention to the location and density of the
thermal vias in Figure 6. The LTM8055 can benefit from
the heat sinking afforded by vias that connect to internal
GND planes at these locations, due to their proximity
to internal power handling components. The optimum
number of thermal vias depends upon the printed
circuit board design. For example, a board might use
very small via holes. It should employ more thermal
vias than a board that uses larger holes.
Hot-Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LTM8055. However, these capacitors
can cause problems if the LTM8055 is plugged into a live
supply (see Linear Technology Application Note 88 for a
complete discussion). The low loss ceramic capacitor
combined with stray inductance in series with the power
source forms an underdamped tank circuit, and the volt-
age at the V_IN pin of the LTM8055 can ring to more than
twice the nominal input voltage, possibly exceeding the
LTM8055’s rating and damaging the part. If the input supply
is poorly controlled or the LTM8055 is hot-plugged into an
energized supply, the input network should be designed
GND
GND/THERMAL VIAS
C_IN
SV_IN
V_IN
R_IN
I_IN
INPUT
SENSE
C_OUT
V_OUT SIGNAL VIA
V_OUT
INPUT
RUN
MODE SYNC
I_OUT
LL
RT FB
R_OUT
OUTPUT
I_OUT
SENSE
GND
V_OUT SIGNAL VIA
8055 F06
Figure 6. Layout Showing Suggested External Components,
GND Plane and Thermal Vias
8055f
16
For more information www.linear.com/LTM8055