LTC6947_15 Datasheet, PDF (16/32 Pages) Linear Technology – Ultralow Noise 0.35GHz to 6GHz Fractional-N Synthesizer

LTC6947
Operation
V_RF+
V_RF+
136Ω
136Ω
RF⁺
12
RF^– ₁₁
MUTE
9
OMUTE
MUTE
RFO[1:0]
6947 F06
Figure 6. Simplified RF Interface Schematic
Serial Port
The SPI-compatible serial port provides control and
monitoring functionality. A configurable status output
STAT gives additional instant monitoring.
Communication Sequence
The serial bus is comprised of CS, SCLK, SDI, and SDO.
Data transfers to the part are accomplished by the se-
rial bus master device first taking CS low to enable the
LTC6947’s port. Input data applied on SDI is clocked on
the rising edge of SCLK, with all transfers MSB first. The
communication burst is terminated by the serial bus master
returning CS high. See Figure 7 for details.
Data is read from the part during a communication burst
using SDO. Readback may be multidrop (more than one
LTC6947 connected in parallel on the serial bus), as SDO
is three-stated (Hi-Z) when CS = 1, or when data is not
being read from the part. If the LTC6947 is not used in
a multidrop configuration, or if the serial port master is
not capable of setting the SDO line level between read
sequences, it is recommended to attach a high value
resistor of greater than 200k between SDO and GND to
ensure the line returns to a known level during Hi-Z states.
See Figure 8 for details.
Single Byte Transfers
The serial port is arranged as a simple memory map, with
status and control available in 15 byte-wide registers. All
data bursts are comprised of at least two bytes. The seven
most significant bits of the first byte are the register address,
with an LSB of 1 indicating a read from the part, and LSB
of 0 indicating a write to the part. The subsequent byte,
or bytes, is data from/to the specified register address.
See Figure 9 for an example of a detailed write sequence,
and Figure 10 for a read sequence.
MASTER–CS
MASTER–SCLK
MASTER–SDI
t_CSS
t_CKL
t_CKH
t_CS
t_CH
DATA
DATA
Figure 7. Serial Port Write Timing Diagram
t_CSS
t_CSH
6947 F07
MASTER–CS
MASTER–SCLK
8TH CLOCK
Hi-Z
LTC6947–SDO
t_DO
t_DO
t_DO
t_DO
DATA
DATA
Hi-Z
6947 F08
Figure 8. Serial Port Read Timing Diagram
6947f
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