LTC6602 Datasheet, PDF (16/28 Pages) Linear Technology – Dual Matched, High Frequency Bandpass/Lowpass Filters

LTC6602
APPLICATIONS INFORMATION
Serial Interface
Connecting SER to ground allows the filter to be controlled
through the SPI serial interface. When CS is low, the serial
data on SDI is shifted into an 8-bit shift-register on the
rising edge of the clock (SCLK), with the MSB transferred
first (see Figure 3). Serial data on SDO is shifted out on
the clock’s falling edge. A high CS will load the 8 bits of
the shift-register into an 8-bit D-latch, which is the serial
control register. The clock is disabled internally when
CS is pulled high. Note: SCLK must be low before CS is
pulled low to avoid an extra internal clock pulse. SDO is
always active in serial mode (never tri-stated) and cannot
be “wire-or’ed” to other SPI outputs. In addition, SDO is
not forced to zero when CS is pulled high.
An LTC6602 may be daisy chained with other LTC6602s
or other devices having serial interfaces. Daisy chain-
ing is accomplished by connecting the SDO of the lead
chip to the SDI of the next chip, while SCLK and CS
remain common to all chips in the daisy chain. The se-
rial data is clocked to all the chips then the CS signal
is pulled high to update all of them simultaneously.
Figure 4 shows an example of two LTC6602s in a daisy
chained SPI configuration.
GAIN1 and GAIN0 are the gain control bits (register bits
D6 and D7 when in serial mode). Their function is shown
in Table 1. In serial mode, register bit D1 can be set to
‘1’ to put the device into a low power shutdown mode.
Register bit D0 is a general purpose output (Pin 21) when
in serial mode.
Table 1. Gain Control
GAIN 1
0
0
1
1
GAIN 0
0
1
0
1
PASSBAND GAIN
(dB)
0
12
24
30
Self-Clocking Operation
The LTC6602 features a unique internal oscillator which sets
the filter cutoff frequency using a single external resistor
connected to the R_BIAS pin. The clock frequency is deter-
mined by the following simple formula (see Figure 5):
f_CLK = 494.1MHz • 10k/R_BIAS
Note: R_BIAS ≤ 200k.
200
175
150
125
100
75
50
20
30 40 50 60 70 80 90
DESIRED CLOCK FREQUENCY (MHz)
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Figure 5. R_BIAS vs Desired Clock Frequency
The design is optimized for V+_A, V+_D = 3V, f_CLK = 90MHz,
where the filter cutoff frequency error is typically <3%
when a 0.1% external 54.9k resistor is used. With differ-
ent resistor values and cutoff frequency control settings
(HPF1, HPF0, LPF1 and LPF0), the highpass and lowpass
cutoff frequencies can be accurately varied from 4.1175kHz
to 90kHz and from 41.175kHz to 900kHz, respectively.
Table 2 summarizes the cutoff frequencies that can be
obtained with an external resistor (R_BIAS) value of 54.9k.
Note that the cutoff frequencies scale with the clock fre-
quency. For example, if HPF1, HPF0, LPF1 and LPF0 are
all equal to zero, and R_BIAS is increased from 54.9k to
200k, f_CLK will decrease from 90MHz to 24.705MHz, the
lowpass cutoff frequency will be reduced from 150kHz
to 41.175kHz, and the highpass cutoff frequency will be
reduced from 15kHz to 4.1175Hz. The cutoff frequencies
that can be obtained with an external resistor value of 200k
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