LTC3355_15 Datasheet, PDF (16/20 Pages) Linear Technology – 20V 1A Buck DC/DC with Integrated SCAP Charger and Backup Regulator

LTC3355
APPLICATIONS INFORMATION
operating conditions, including load current, input voltage
and temperature. Figure 2 shows an equivalent circuit for
the boost regulator control loop. The error amplifier is a
transconductance amplifier with a finite output impedance.
The power section consisting of a modulator, power switch
and inductor, is modeled as a transconductance amplifier
generating an output current proportional to the voltage
at the V_CBST pin. Note that the output capacitor integrates
this current, and that the capacitor on the V_CBST pin (C_C)
integrates the error amplifier output current, resulting in
two poles in the loop. In most cases a zero is required
and comes from either the ESR of the output capacitor or
from a resistor R_C in series with C_C. This simple model
works well as long as the inductor value is not too high
and the loop crossover frequency is much lower than the
switching frequency. A phase lead capacitor across the
feedback divider may improve the transient response. A
small capacitor from V_CBST to ground may have to be
added if phase lead is used.
Low Ripple Burst Mode Operation
To enhance efficiency at light loads the buck and boost
regulator can run in low ripple Burst Mode operation which
keeps the output capacitor charged to the proper voltage
while minimizing the input quiescent current. Setting the
MODE pin high sets both the buck and boost into Burst
Mode operation. During Burst Mode operation, the enabled
regulator delivers single cycle bursts of current to the out-
put capacitor followed by sleep periods where the power
is delivered to the load by the output capacitor. Since the
power to the output is delivered with single, low current
pulses, the output ripple is kept below 15mV for typical
applications. As the load current falls towards a no-load
condition, the percentage of time in sleep mode increases
and the average input current is greatly reduced resulting
in high efficiency even at very light loads. At higher load
currents the regulators will seamlessly transition into
PWM mode.
BOOST LOOP
CURRENT MODE POWER STAGE
g_m = 4mhos
g_m = 27μS
32M
V_{CBST GND}
SW2
FB
0.8V
R1
C_PL
ESR
C_OUT
R2
POLYMER,
TANTALUM
OR
ELECTROLYTIC
OUTPUT
C_OUT
CERAMIC
R_C
C_F
C_C
3355 F02
Figure 2. Model for Boost Loop Response
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