LTC3108-1_12 Datasheet, PDF (16/24 Pages) Linear Technology – Ultralow Voltage Step-Up Converter

LTC3108-1
APPLICATIONS INFORMATION
at times when the input power may be lost. Note that this
capacitor can charge all the way to 5.25V (regardless of
the settings for V_OUT), so ensure that the holdup capacitor
has a working voltage rating of at least 5.5V at the tem-
perature for which it will be used. The VSTORE capacitor
can be sized using the following:
C_STORE
≥
[^6μA
+ I_Q
+I_LDO +(I_BURST • t
5.25 − V_OUT
•
f)_]
•
TSTORE
Where 6μA is the quiescent current of the LTC3108-1, I_Q
is the load on V_OUT in between bursts, I_LDO is the load on
the LDO between bursts, I_BURST is the total load during
the burst, t is the duration of the burst, f is the frequency
of the bursts, TSTORE is the storage time required and
V_OUT is the output voltage required.
To minimize losses and capacitor charge time, all capaci-
tors used for V_OUT and VSTORE should be low leakage.
See Table 6 for recommended storage capacitors.
Table 6. Recommended Storage Capacitors
VENDOR
PART NUMBER/SERIES
AVX
www.avx.com
Cap-XX
www.cap-xx.com
BestCap Series
TAJ and TPS Series Tantalum
GZ Series
Cooper/Bussmann
KR Series
www.bussmann.com/3/PowerStor.html P Series
Vishay/Sprague
www.vishay.com/capacitors
Tantamount 592D
595D Tantalum
150CRZ/153CRV Aluminum
013 RLC (Low Leakage)
Storage capacitors requiring voltage balancing are not
recommended due to the current draw of the balancing
resistors.
PCB Layout Guidelines
Due to the rather low switching frequency of the resonant
converter and the low power levels involved, PCB layout
is not as critical as with many other DC/DC converters.
There are, however, a number of things to consider.
Due to the very low input voltage the circuit may operate
from, the connections to V_IN, the primary of the transformer
and the SW and GND pins of the LTC3108-1 should be
designed to minimize voltage drop from stray resistance
and able to carry currents as high as 500mA. Any small
voltage drop in the primary winding conduction path will
lower efficiency and increase capacitor charge time.
Also, due to the low charge currents available at the outputs
of the LTC3108-1, any sources of leakage current on the
output voltage pins must be minimized. An example board
layout is shown in Figure 3.
V_IN
V_OUT
V_OUT2
VAUX
1
VSTORE
V_OUT
V_OUT2
2
3
4
VLDO
5
VLDO
PGD
PGOOD
6
31081 FO3
GND
SW
12
C2
11
C1
10
9
V_{OUT2_EN}
VS1
8
VS2
7
VIAS TO GROUND PLANE
Figure 3. Example Component Placement for
Two-Layer PC Board (DFN Package)
31081fa
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