LTC1605-1_15 Datasheet, PDF (16/20 Pages) Linear Technology – Single Supply 16-Bit, 100ksps, Sampling ADCs

LTC1605-1/LTC1605-2
TYPICAL APPLICATIO S
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* Start GETDATA Routine
*
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*
ORG $C000 Program start location
INIT1 LDAA #$03 0,0,0,0,0,0,1,1
*
“STAF=0,STAI=0,CWOM=0,HNDS=0, OIN=0, PLS=0, EGA=1,INVB=1”
STAA PIOC Ensures that the PIOC register’s status is the same
*
as after a reset, necessary of simple Port D manipulation
LDAA #$00 0,0,0,0,0,0,0,0
*
“Bits 7 - 0 are used as inputs for the LTC1605’s data
STAA DDRC Direction of PortD’s bit are now set as inputs
LDAA #$2F -,-,1,0;1,1,1,1
*
-, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
STAA PORTD Keeps SS* a logic high when DDRD, Bit5 is set
LDAA #$38 -,-,1,1;1,0,0,0
STAA DDRD SS* , SCK, MOSI are configured as Outputs
*
MISO, TxD, RxD are configured as Inputs
* DDRD’s Bit5 is a 1 so that port D’s SS* pin is a general output
LDAA #$50
STAA SPCR The SPI is configured as Master, CPHA = 0, CPOL = 0
*
and the clock rate is E/2
*
(This assumes an E-Clock frequency of 4MHz. For higher
*
E-Clock frequencies, change the above value of $50 to a
*
value that ensures the SCK frequency is 2MHz or less.)
GETDATAPSHX
PSHY
PSHA
*
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* Setup indecies
*
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*
LDX #$0 The X register is used as a pointer to the memory
*
locations that hold the conversion data
LDY #$1000
*
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* Ensure that a logic high is applied
*
* to the LTC1391’s /CS and the
*
* LTC1605’s R/C pins
*
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*
BSET PORTD,Y %00100000 This sets the SS* output bit to a logic
*
high, ensuring that the LTC1391’s CS*
*
input is a logic high while clocking
*
MUX address data into the LTC1391
BSET PORTA,Y %00010000 This sets the R/C* output bit to a logic
*
high, ensuring that the LTC1605’s R/C*
*
input is a logic high before initiating
*
a conversion
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