LT3840_15 Datasheet, PDF (16/24 Pages) Linear Technology – Wide Input Range Synchronous Regulator Controller with Accurate Current Limit

LT3840
Applications Information
the bulk capacitance and RMS current capability. The bulk
capacitance will determine the supply input ripple voltage.
The RMS current capability is used to prevent overheating
the capacitor. The bulk capacitance is calculated based on
maximum input ripple, ΔV_IN:
C_IN(BULK)
=
I_OUT(MAX)
ΔV_IN • f_SW •
• V_OUT
V_IN(MIN)
ΔV_IN is typically chosen at a level acceptable to the user.
A good starting point is 100mV to 200mV. Aluminum
electrolytic capacitors are a good choice for high voltage,
bulk capacitance due to their high capacitance per unit area.
The capacitor’s RMS current is:
I_CIN(RMS) =I_OUT
V_OUT(V_IN – V_OUT)
(V_IN )²
If applicable, calculate it at the worst-case condition,
V_IN = 2V_OUT. The RMS current rating of the capacitor
is specified by the manufacturer and should exceed the
calculated I_CIN(RMS). Due to their low ESR (equivalent
series resistance), ceramic capacitors are a good choice
for high voltage, high RMS current handling. Note that the
ripple current ratings from aluminum electrolytic capacitor
manufacturers are based on 2000 hours of life. This makes
it advisable to further derate the capacitor or to choose
a capacitor rated at a higher temperature than required.
The combination of aluminum electrolytic capacitors and
ceramic capacitors is an economical approach to meeting
the input capacitor requirements. The capacitor voltage
rating must be rated greater than maximum V_IN voltage.
Multiple capacitors may also be paralleled to meet size
or height requirements in the design. Locate the capaci-
tor very close to the MOSFET switch and use short, wide
PCB traces to minimize parasitic inductance. Use a small
(0.1μF to 1μF) bypass capacitor between the chip V_IN pin
and GND, placed close to the LT3840.
Output Capacitor Selection
The output capacitance, C_OUT, selection is based on the
design’s output voltage ripple, ΔV_OUT and transient load
requirements. ΔV_OUT is a function of ΔI_L and the C_OUT
ESR. It is calculated by:
∆V_OUT
=
∆I_L
•
_ESR

+
(8
•
1
f_SW •
C_OUT
)


The maximum ESR required to meet a ΔV_OUT design
requirement can be calculated by:
ESR(MAX)= ^{(∆VOUT)(L)(fSW)}
V_OUT
•
_1–
V_{OUT }
V_{IN(MAX)}
Worst-case ΔV_OUT occurs at the highest input voltage. Use
paralleled multiple capacitors to meet the ESR require-
ments. Increasing the inductance is an option to lower the
ESR requirements. For extremely low ΔV_OUT, an additional
LC filter stage can be added to the output of the supply.
Linear Technology’s Application Note 44 has some good
tips on sizing an additional output filter.
Output Voltage Programming
A resistive divider sets the DC output voltage according
to the following formula:
R2
=
R1
 V_OUT
_1.250V
–
1^
The external resistor divider is connected to the output of
the converter as shown in Figure 6.
L1
R2
FB
R1
VOUT
COUT
3840 F06
Figure 6. Output Voltage Feedback Divider
Tolerance of the feedback resistors will add additional er-
ror to the output voltage. The V_FB pin input bias current
is typically 5nA, so use of extremely high value feedback
resistors results in a converter output that is slightly
3840fa
16
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