LT3837 Datasheet, PDF (16/28 Pages) Linear Technology – Isolated No-Opto Synchronous Flyback Controller

LT3837
APPLICATIONS INFORMATION
Optimization might show that a more efficient solution
is obtained at higher peak current but lower inductance
and the associated winding series resistance. A simple
spreadsheet program is useful for looking at tradeoffs.
Transformer Core Selection
Once L_P is known, the type of transformer is selected.
High efficiency converters use ferrite cores to minimize
core loss. Actual core loss is independent of core size for
a fixed inductance, but decreases as inductance increases.
Since increased inductance is accomplished through
more turns of wire, copper losses increase. Thus trans-
former design balances core and copper losses. Remem-
ber that increased winding resistance will degrade cross
regulation and increase the amount of load compensa-
tion required.
The main design goals for core selection are reducing
copper losses and preventing saturation. Ferrite core mate-
rial saturates hard, rapidly reducing inductance when the
peak design current is exceeded. This results in an abrupt
increase in inductor ripple current and, consequently, out-
put voltage ripple. Do not allow the core to saturate! The
maximum peak primary current occurs at minimum V_IN:
I_PK
=
P_IN
V_IN(MIN) • DC_MAX
•
⎛
⎝⎜
1+
X_MIN
2
⎞
⎠⎟
now :
DC_MAX
=
1+
1
N • V_IN(MIN)
V_OUT
=
1+
1
1•
3
9
3.3
= 52.4%
( ) ( ) _{XMIN =}
V_IN(MIN) • DC_MAX
f_OSC • L_P • P_IN
2
9 • 0.52 ²
=
200kHz • 7.8μH • 37.5W
= 0.380
Using the example numbers leads to:
I_PK
=
37.5W
9V • 0.524
•
⎛
⎝⎜
1+
0.380 ⎞
2 ⎠⎟
=
9.47A
16
Multiple Outputs
One advantage that the flyback topology offers is that ad-
ditional output voltages can be obtained simply by adding
windings. Designing a transformer for such a situation is
beyond the scope of this document. For multiple windings,
realize that the flyback winding signal is a combination of
activity on all the secondary windings. Thus load regulation
is affected by each windings load. Take care to minimize
cross regulation effects.
Setting Feedback Resistive Divider
Use the equation developed in the Operation section for
the feedback divider.
It is recommended that the Thevenin impedance of the
resistors on the FB Pin is roughly 3k for bias current
cancellation and other reasons.
For the example using primary winding sensing if
ESR = 0.002 and R_DS(ON) = 0.004 then:
( ) _R1=
3k
1.237
•
⎡⎛
⎣⎢⎢⎝⎜
3.3 + 10•(0.002 + 0.004
(1/ 3)
⎞⎤
⎟
⎠
–
0.7⎥
⎦⎥
=
22.75k
So, choose 22.1k.
Current Sense Resistor Considerations
The external current sense resistor is used to control peak
primary switch current, which controls a number of key
converter characteristics including maximum power and
external component ratings. Use a noninductive current
sense resistor (no wire-wound resistors). Mounting the
resistor directly above an unbroken ground plane con-
nected with wide and short traces keeps stray resistance
and inductance low.
The dual sense pins allow for a fully Kelvined connection.
Make sure that SENSE⁺ and SENSE^– are isolated and con-
nect close to the sense resistor to preserve this.
Peak current occurs at 98mV of sense voltage V_SENSE. So
the nominal sense resistor is V_SENSE/I_PK. For example, a
peak switch current of 10A requires a nominal sense resistor
of 0.010Ω. Note that the instantaneous peak power in the
sense resistor is 1W, and that it is rated accordingly. The
use of parallel resistors can help achieve low resistance,
low parasitic inductance and increased power capability.
3837fa