LT3061_15 Datasheet, PDF (16/20 Pages) Linear Technology – 45V VIN, Micropower, Low Noise, 100mA LDO with Output Discharge

LT3061
Applications Information
Table 2. Measured Thermal Resistance for DFN Package
COPPER AREA
TOPSIDE* BACKSIDE BOARD AREA THERMAL RESISTANCE
(mm²)
(mm²)
(mm²)
(JUNCTION-TO-AMBIENT)
2500
2500
2500
38°C/W
1000
2500
2500
38°C/W
225
2500
2500
40°C/W
100
2500
2500
45°C/W
*Device is mounted on topside
Table 3. Measured Thermal Resistance for MSOP Package
COPPER AREA
TOPSIDE* BACKSIDE BOARD AREA THERMAL RESISTANCE
(mm²)
(mm²)
(mm²)
(JUNCTION-TO-AMBIENT)
2500
2500
2500
29°C/W
1000
2500
2500
30°C/W
225
2500
2500
32°C/W
100
2500
2500
45°C/W
*Device is mounted on topside
Calculating Junction Temperature
Example: Given an output voltage of 2.5V, an input volt-
age range of 12V ±5%, an output current range of 0mA
to 50mA and a maximum ambient temperature of 85°C,
what will the maximum junction temperature be?
The power dissipated by the device equals:
I_OUT(MAX) • (V_IN(MAX)–V_OUT) + I_GND • V_IN(MAX)
where,
I_OUT(MAX) = 50mA
V_IN(MAX) = 12.6V
I_GND at (I_OUT = 50mA, V_IN = 12V) = 1mA
So,
P = 50mA • (12.6V – 2.5V) + 1mA • 12.6V = 0.518W
Using a DFN package, the thermal resistance will be in
the range of 38°C/W to 45°C/W depending on the copper
area. So the junction temperature rise above ambient will
be approximately equal to:
0.518W • 45°C/W = 23.3°C
The maximum junction temperature equals the maximum
ambient temperature plus the maximum junction tempera-
ture rise above ambient or:
T_JMAX = 85°C + 23.3°C = 108.3°C
Output Discharge
The LT3061 includes a low resistance medium voltage
NMOS device which rapidly discharges the output voltage
if the part is put in shutdown mode. For a 2.9V output
with a 10μF decoupling capacitor, this NMOS discharges
the output to 290mV in 750µs if SHDN is driven low.
Control circuitry drives the gate of the NMOS high if either
the SHDN pin or the IN pin are driven low. In the case
where the IN pin is driven to ground, the NMOS rapidly
discharges the OUT pin to the threshold voltage of the
NMOS, about 800mV. From 800mV, the external load
will continue to discharge the OUT pin at a reduced rate.
The control circuitry implements protection features which
allow the OUT pin to be driven from –1V to 20V without
damaging the LT3061. Current limit foldback for output
voltages greater than 6V protects the NMOS pull-down,
but increases discharge time for higher output voltages.
4.0
C_OUT = 10µF
3.5 ^{VIN = VOUT +1V}
3.0
2.5
2.0
1.5
1.0
OUTPUT DISCHARGE
FOLDBACK STARTS
0.5
0
0 2 4 6 8 10 12 14 16 18 20
OUTPUT VOLTAGE (V)
3061 F07
Figure 7. Discharge Time vs Output Voltage
3061f
16
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