LTC6401-20 Datasheet, PDF (15/16 Pages) Linear Technology – 1.3GHz Low Noise, Low Distortion Differential ADC Driver for 140MHz IF

LTC6401-20
TYPICAL APPLICATION
Test Circuit B, 4-Port Analysis
V⁺
1000pF
0.1μF
V–
12
ENABLE
V⁺
11
10
V–
9
PORT 1
(50Ω)
1/2
AGILENT
E5O71A
0.1μF
200Ω
+IN
13
+IN
14
–IN
15
PORT 2
(50Ω)
0.1μF
–IN
16
R_G
100Ω
BIAS CONTROL
R_F
1000Ω
IN+
OUT–
IN–
OUT+
R_G
100Ω
R_F
1000Ω
COMMON
MODE CONTROL
R_OUT
12.5Ω
R_FILT
50Ω
R_FILT
50Ω
R_OUT
12.5Ω
+OUT _37.4Ω
8
+OUTF
7
0.1μF
C_FILT
1.7pF –OUTF
6
PORT 3
(50Ω)
1/2
AGILENT
E5O71A
–OUT _37.4Ω
5
0.1μF
PORT 4
(50Ω)
1
V⁺
1000pF
2
V_OCM
3
V⁺
0.1μF
0.1μF
V_OCM ^V+
4 _V–
640120 TA02
PACKAGE DESCRIPTION
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
3.50 ± 0.05
1.45 ± 0.05
2.10 ± 0.05 (4 SIDES)
0.70 ±0.05
3.00 ± 0.10
(4 SIDES)
PIN 1
TOP MARK
(NOTE 6)
0.75 ± 0.05
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
15 16
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
0.40 ± 0.10
1
1.45 ± 0.10
2
(4-SIDES)
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
(UD16) QFN 0904
0.25 ± 0.05
0.50 BSC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
640120f
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