LTC3548A_15 Datasheet, PDF (15/20 Pages) Linear Technology – Dual Synchronous 400mA/800mA, 2.25MHz Step-Down DC/DC Regulator

LTC3548A
APPLICATIONS INFORMATION
4. Keep sensitive components away from the SW pins.
The input capacitor, C_IN, and the resistors R1 to R4
should be routed away from the SW traces and the
inductors.
5. A ground plane is preferred, but if not available keep
the signal and power grounds segregated with small-
signal components returning to the GND pin at one
point. Additionally the two grounds should not share
the high current paths of C_IN or C_OUT.
6. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to V_IN or GND.
V_OUT2
V_IN
C_IN
RUN/SS2 V_IN RUN/SS1
L2
MODE/SYNC
POR
L1
SW2
SW1
C5
LTC3548A
C4
V_OUT1
R4
C_OUT2
V_FB2
V_FB1
GND
R3
R2
R1
C_OUT1
BOLD LINES INDICATE HIGH CURRENT PATHS
3548A F02
Figure 2. LTC3548A Layout Diagram (See Board Layout Checklist)
V_IN
2.5V TO 5.5V
C1
10μF
V_OUT2
2.5V
400mA
L2
4.7μH
C5 22pF
RUN/SS2 V_IN RUN/SS1
MODE/SYNC
POR
SW2 LTC3548A SW1
R5
100k
POWER-ON
L1 ^RESET
2.2μH
C4 22pF
V_OUT1
1.8V
800mA
C3
4.7μF
R4
887k
V_FB2
V_FB1
R3
GND
280k
R1
R2
301k ^604k
C1, C2, C3: TAIYO YUDEN JMK316BJ106MD
L1: TDK VLF3010AT-2R2M1R0-1
L2: TDK VLF3010AT-4R7MR70-1
C2
10μF
3548 F03a
Figure 3. 1mm Height Core Supply
Efficiency vs Load Current
100
90 ^2.5V
80
1.8V
70
60
50
40
30
20 _{VIN = 3.3V}
10 ^{Burst Mode OPERATION}
NO LOAD ON OTHER CHANNEL
0
1
10
100
LOAD CURRENT (mA)
1000
3548A F03b
3548afa
15