LTC2452_15 Datasheet, PDF (15/22 Pages) Linear Technology – Ultra-Tiny, Differential, 16-Bit ADC with SPI Interface

LTC2452
Applications Information
A 0.1µF, high quality, ceramic capacitor in parallel with a
10µF ceramic capacitor should be connected between the
REF and GND pins, as close as possible to the package.
The 0.1µF capacitor should be placed closest to the ADC.
Driving V_IN+ and V_IN–
The input drive requirements can best be analyzed using
the equivalent circuit of Figure 16. The input signal V_SIG is
connected to the ADC input pins (IN⁺ and IN^–) through an
equivalent source resistance R_S. This resistor includes both
the actual generator source resistance and any additional
optional resistors connected to the input pins. Optional
input capacitors C_IN are also connected to the ADC input
pins. This capacitor is placed in parallel with the ADC
input parasitic capacitance C_PAR. Depending on the PCB
layout, C_PAR has typical values between 2pF and 15pF. In
addition, the equivalent circuit of Figure 16 includes the
converter equivalent internal resistor R_SW and sampling
capacitor C_EQ.
There are some immediate trade-offs in R_S and C_IN without
needing a full circuit analysis. Increasing R_S and C_IN can
give the following benefits:
1) Due to the LTC2452’s input sampling algorithm, the input
current drawn by either V_IN+ or V_IN– over a conversion
cycle is typically 50nA. A high R_S • C_IN attenuates the
high frequency components of the input current, and
R_S values up to 1k result in <1LSB error.
2) The bandwidth from V_SIG is reduced at the input pins
(IN⁺, IN^–). This bandwidth reduction isolates the ADC
from high frequency signals, and as such provides
simple anti-aliasing and input noise reduction.
3) Switching transients generated by the ADC are attenu-
ated before they go back to the signal source.
4) A large C_IN gives a better AC ground at the input pins,
helping reduce reflections back to the signal source.
5) Increasing R_S protects the ADC by limiting the current
during an outside-the-rails fault condition.
There is a limit to how large R_S • C_IN should be for a given
application. Increasing R_S beyond a given point increases
the voltage drop across R_S due to the input current,
to the point that significant measurement errors exist.
Additionally, for some applications, increasing the R_S • C_IN
product too much may unacceptably attenuate the signal
at frequencies of interest.
For most applications, it is desirable to implement C_IN as
a high-quality 0.1µF ceramic capacitor and R_S ≤ 1k. This
capacitor should be located as close as possible to the
actual V_IN package pin. Furthermore, the area encompassed
by this circuit path, as well as the path length, should be
minimized.
R_S
SIG^{+ +–}
R_S
SIG^{– +–}
V_CC
I_LEAK
IN⁺
R_SW
15k
(TYP)
C_IN
I_LEAK
C_PAR
C_EQ
0.35pF
(TYP)
V_CC
I_LEAK
IN^–
R_SW
15k
(TYP)
C_IN
I_LEAK
C_PAR
C_EQ
0.35pF
(TYP)
I_CONV
I_CONV
2452 F16
Figure 16. LTC2452 Input Drive Equivalent Circuit
For more information www.linear.com/LTC2452
2452fd
15