LTC2440_15 Datasheet, PDF (15/28 Pages) Linear Technology – 24-Bit High Speed Differential ADC with Selectable Speed/Resolution

APPLICATIONS INFORMATION
4.5V TO 5.5V
1μF
2
V_CC
BUSY ¹⁵
REFERENCE VOLTAGE
0.1V TO V_CC
ANALOG INPUT RANGE
–0.5V_REF TO 0.5V_REF
3
LTC2440
REF⁺
f_O
14
4 _REF–
SCK ¹³
5 _IN+
SDO ¹²
6 _IN–
CS ¹¹
7
SDI
1, 8, 9, 16 _GND
EXT ¹⁰
LTC2440
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
3-WIRE
SPI INTERFACE
V_CC
200nV NOISE, 50/60Hz REJECTION
10-SPEED/RESOLUTION PROGRAMMABLE
2μV NOISE, 880Hz OUTPUT RATE
CS
TEST EOC
SDO
Hi-Z
SCK
(EXTERNAL)
TEST EOC
Hi-Z
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 5
LSB
BIT 0
SUB LSB
TEST EOC
Hi-Z
BUSY
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
2440 F05
Figure 5. External Serial Clock, Single Cycle Operation
EOC = 1 (BUSY = 1) while a conversion is in progress
and EOC = 0 (BUSY = 0) if the device is in the sleep state.
Independent of CS, the device automatically enters the low
power sleep state once the conversion is complete.
When the device is in the sleep state (EOC = 0), its con-
version result is held in an internal static shift register.
The device remains in the sleep state until the first rising
edge of SCK is seen. Data is shifted out the SDO pin on
each falling edge of SCK. This enables external circuitry
to latch the output on the rising edge of SCK. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. On the 32nd falling edge of SCK, the device
begins a new conversion. SDO goes HIGH (EOC = 1) and
BUSY goes HIGH indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z
and BUSY monitored for the completion of a conversion.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status on the SDO pin.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the fifth falling edge (SDI must
be properly loaded each cycle) and the 32nd falling edge
of SCK, see Figure 6. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32-bits of output data, aborting an invalid conversion
cycle or synchronizing the start of a conversion.
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface.
The conversion result is shifted out of the device by an
externally generated serial clock (SCK) signal, see Figure
7. CS may be permanently tied to ground, simplifying the
user interface or isolation barrier. The external serial clock
mode is selected by tying EXT LOW.
Since CS is tied LOW, the end-of-conversion (EOC) can
be continuously monitored at the SDO pin during the
convert and sleep states. Conversely, BUSY (Pin 15) may
be used to monitor the status of the conversion cycle.
EOC or BUSY may be used as an interrupt to an external
2440fd
15