LTC2281 Datasheet, PDF (15/24 Pages) Linear Technology – Dual 10-Bit, 125Msps Low Power 3V ADC

LTC2281
APPLICATIONS INFORMATION
Reference Operation
Figure 9 shows the LTC2281 reference circuitry consisting
of a 1.5V bandgap reference, a difference amplifier and
switching and control circuit. The internal voltage reference
can be configured for two pin selectable input ranges of
2V (±1V differential) or 1V (±0.5V differential). Tying the
SENSE pin to V_DD selects the 2V range; tying the SENSE
pin to V_CM selects the 1V range.
The 1.5V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to gener-
ate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required
for the 1.5V reference output, V_CM. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
LTC2281
1.5V
V_CM
4W
1.5V BANDGAP
REFERENCE
2.2μF
1V 0.5V
TIE TO V_DD FOR 2V RANGE;
TIE TO V_CM FOR 1V RANGE;
RANGE = 2 • V_SENSE FOR
0.5V < V_SENSE < 1V
SENSE
1μF
REFH
RANGE
DETECT
AND
CONTROL
BUFFER
INTERNAL ADC
HIGH REFERENCE
2.2μF
1μF
0.1μF
REFL
DIFF AMP
INTERNAL ADC
LOW REFERENCE
2281 F09
Figure 9. Equivalent Reference Circuit
The difference amplifier generates the high and low
reference for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins. The multiple output
pins are needed to reduce package inductance. Bypass
capacitors must be connected as shown in Figure 9. Each
ADC channel has an independent reference with its own
bypass capacitors. The two channels can be used with the
same or different input ranges.
Other voltage ranges between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 10. An external reference can be used by ap-
plying its output directly or through a resistor divider to
SENSE. It is not recommended to drive the SENSE pin
with a logic device. The SENSE pin should be tied to the
appropriate level as close to the converter as possible. If
the SENSE pin is driven externally, it should be bypassed
to ground as close to the device as possible with a 1μF
ceramic capacitor. For the best channel matching, connect
an external reference to SENSEA and SENSEB.
1.5V
12k
0.75V
12k
V_CM
2.2μF
SENSE
1μF
LTC2281
2281 F10
Figure 10. 1.5V Range ADC
Input Range
The input range can be set based on the application.
The 2V input range will provide the best signal-to-noise
performance while maintaining excellent SFDR. The 1V
input range will have better SFDR performance, but the
SNR will degrade by 0.9dB. See the Typical Performance
Characteristics section.
Driving the Clock Input
The CLK inputs can be driven directly with a CMOS or
TTL level signal. A sinusoidal clock can also be used
along with a low jitter squaring circuit before the CLK pin
(Figure 11).
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