LTC1746 Datasheet, PDF (15/20 Pages) Linear Technology – Low Power,14-Bit, 25Msps ADC

LTC1746
APPLICATIO S I FOR ATIO
Input Range
The input range can be set based on the application. For
oversampled signal processing in which the input fre-
quency is low (<10MHz), the largest input range will
provide the best signal-to-noise performance while main-
taining excellent SFDR. For high input frequencies
(>10MHz), the 2V range will have the best SFDR perfor-
mance but the SNR will degrade by 3.5dB. See the Typical
Performance Characteristics section.
Driving the Encode Inputs
The noise performance of the LTC1746 can depend on the
encode signal quality as much as on the analog input. The
ENC/ENC inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a 2V
bias. The bias resistors set the DC operating point for
transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
LTC1746
5V
CLOCK
INPUT
ANALOG INPUT
0.1µF
1:4
50Ω
V_DD
ENC
2V BIAS
6k
V_DD
ENC
2V BIAS
6k
BIAS
TO INTERNAL
ADC CIRCUITS
1746 F07
Figure 7. Transformer Driven ENC/ENC with Equivalent Encode Input Circuit
ENC
V_THRESHOLD = 2V
2V ENC ^LTC1746
0.1µF
1746 F08a
Figure 8a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
3.3V
MC100LVELT22 ^3.3V _130Ω
Q0
D0
130Ω
ENC
Q0
83Ω
ENC ^LTC1746
83Ω
1746 F08b
Figure 8b. ENC Drive Using a CMOS-to-PECL Translator
1746f
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