LTC1704_15 Datasheet, PDF(15/28 Page) Linear Technology – 550kHz Synchronous Switching Regulator Controller Plus Linear Regulator Controller

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LTC1704_15 Datasheet, PDF (15/28 Pages) Linear Technology – 550kHz Synchronous Switching Regulator Controller Plus Linear Regulator Controller

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LTC1704/LTC1704B

APPLICATIO S I FOR ATIO

across the inductor will be zero, and the inductor current

remains zero. This prevents current from flowing back-

wards in QB, eliminating that power loss term. It also

reduces the ripple current in the inductor as the output

current approaches zero.

IRIPPLE

IAVERAGE

TIME

Figure 5a. Continous Mode

IRIPPLE

TIME

Figure 5b. Burst Mode Operation

IAVERAGE

1704 F05

The LTC1704B does not shift into Burst Mode operation at

light loads, eliminating low frequency output ripple at the

expense of light load efficiency.

The LTC1704 detects when the inductor current has

reached zero by monitoring the voltage at the SW pin while

QB is on (see BURST in Block Diagram). Since QB acts like

a resistor, SW should ideally be right at 0V when the

inductor current reaches zero. In reality, the SW node will

ring to some degree immediately after it is switched to

ground by QB, causing some uncertainty as to the actual

moment the average current in QB goes to zero. The

LTC1704 minimizes this effect by turning on the Burst

Comparator only at the last 180ns of the switching period,

before QB turns off. In addition, the Burst Comparator is

disabled if QB turns on for less than 200ns. Despite this,

care must still be taken in the PCB layout to ensure that

proper kelvin sensing for the SW pin is provided. Connect

the SW pin of the LTC1704 as close to the drain of QB as

possible through a thick trace. The same applies to the

PGND pin of the LTC1704, which is the negative input of

the burst comparator and it should be connected close to

the source of QB through a thick trace. Ringing on the

PGND pin due to an insufficient PVCC bypass capacitor can

also cause the burst comparator to trip prematurely.

Connect at least a 10ÂµF bypass capacitor directly from the

PVCC pin to PGND.

The burst comparator is turned on only at the last 180ns

of the switching period, the propagation delay of the

comparator is designed to be fast so that a zero or low

positive voltage on the SW node can trip the comparator

within this 180ns. Low inductor ripple current coupled

with low MOSFET RDS(ON) may prolong the delay of the

burst comparator and prevent the comparator from trip-

ping. To overcome this, reduce the inductor value to

increase the ripple current and the SW node voltage

change.

The moment LTC1704 (non-B parts) enters Burst Mode

operation, both drivers skip several switching cycles until

the output droops. Once the voltage feedback loop requests

for an additional 10% duty cycle, the LTC1704 enters Con-

tinuous mode operation again. To eliminate audible noise

from certain types of inductors when they are lightly loaded,

LTC1704 includes an internal timer that forces Continuous

mode operation every 15Âµs.

In Burst Mode operation, both resistive loss and switching

loss are minimized while keeping the output in regulation.

The total deviation from the regulated output is within the

1.5% regulation tolerance of the LTC1704. As the load

current falls to zero in Burst Mode operation, the most

significant loss term becomes the 4.5mA quiescent cur-

rent drawn by the LTC1704âusually much less than the

minimum load current in a typical low voltage logic sys-

tem. Burst Mode operation maximizes efficiency at low load

currents, but can cause low frequency ripple in the output

voltage as the cycle-skipping circuitry switches on and off.

VSW

TIME

VBG

BURST

COMPARATOR

DISABLED IF QB

TURNS ON FOR

LESS THAN 200ns

BURST

COMPARATOR

TURNS ON

180ns BEFORE

QB TURNS OFF

TIME

1704 F06

Figure 6. Burst Comparator Turns On 180ns Before QB Turns Off

1704bfa

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