LTC1417 Datasheet, PDF (15/32 Pages) Linear Technology – Low Power 14-Bit, 400ksps Sampling ADC Converter with Serial I/O

APPLICATIONS INFORMATION
LTC1417
1 _AIN+
LTC1417
ANALOG
INPUT
+–
CIRCUITRY
A_{IN– VREF}
2
3
REFCOMP AGND
4
5
1µF
10µF
V_SS
15
10µF
V_DD
16
DGND
10
10µF
DIGITAL
SYSTEM
ANALOG GROUND PLANE
1417 F12
Figure 12. Power Supply Grounding Practice
wait state during conversion or by using three-state buff-
ers to isolate the ADC data bus. The traces connecting the
pins and bypass capacitors must be kept short and should
be made as wide as possible.
The LTC1417 has differential inputs to minimize noise
coupling. Common mode noise on the A_IN+ and A_IN– leads
will be rejected by the input CMRR. The A_IN– input can be
used as a ground sense for the A_IN+ input; the LTC1417 will
hold and convert the difference voltage between A_IN+ and
A_IN–. The leads to A_IN+ (Pin 1) and A_IN– (Pin 2) should be
kept as short as possible. In applications where this is not
possible, the A_IN+ and A_IN– traces should be run side by
side to equalize coupling.
SUPPLY BYPASSING
High quality, low series resistance ceramic, 10µF bypass
capacitors should be used at the V_DD and REFCOMP pins.
Surface mount ceramic capacitors such as Taiyo Yuden
LMK325BJ106MN provide excellent bypassing in a small
board space. Alternatively 10µF tantalum capacitors in
parallel with 0.1µF ceramic capacitors can be used.
Bypass capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypass
capacitors must be kept short and should be made as wide
as possible.
Example Layout
Figures 13a, 13b, 13c and 13d show the schematic and
layout of a suggested evaluation board. The layout demon-
strates the proper use of decoupling capacitors and ground
plane with a 2-layer printed circuit board.
POWER SHUTDOWN
The LTC1417 provides two power shutdown modes, Nap
and Sleep, to save power during inactive periods. The
Nap mode reduces ADC power dissipation by 80% and
leaves only the digital logic and reference powered up.
The wake-up time from Nap to active is 500ns (see Figure
14). In Sleep mode, all bias currents are shut down and
only leakage current remains— about 2µA. Wake-up
time from Sleep mode is much slower since the reference
circuit must power up and settle to 0.005% for full 14-bit
accuracy. Sleep mode wake-up time is dependent on the
value of the capacitor connected to the REFCOMP (Pin 4).
The wake-up time is 30ms with the recommended 10µF
capacitor. Shutdown is controlled by Pin 11 (SHDN); the
ADC is in shutdown when it is low. The shutdown mode
is selected with Pin␣ 12 (RD); low selects Nap mode, high
selects Sleep mode.
SHDN
t₁
CONVST
1417 F14
Figure 14. SHDN to CONVST Wake-Up Timing
15