LTC1285_15 Datasheet, PDF (15/24 Pages) Linear Technology – 3V Micropower Sampling 12-Bit A/D Converters in SO-8 Packages

LTC1285/LTC1288
APPLICATION INFORMATION
of Maximum Clock Rate vs Supply Voltage). If the maxi-
mum clock frequency is used, care must be taken to
ensure that the device converts correctly.
Mixed Supplies
It is possible to have a microprocessor running off a 5V
supply and communicate with the LTC1285/LTC1288
operating on a 3V supply. The inputs of CS, CLK and D_IN
of the LTC1285/LTC1288 have no problem to take a
voltage swing from 0V to 5V. With the LTC1285 operating
on a 3V supply, the output of D_OUT may only go between
0V and 3V. The 3V output level is higher enough to trip a
TTL input of the MPU. Figure 6 shows a 3V powered
LTC1285 interfacing a 5V system.
3V ^4.7µF
BOARD LAYOUT CONSIDERATIONS
Grounding and Bypassing
The LTC1285/LTC1288 are easy to use if some care is
taken. They should be used with an analog ground plane
and single point grounding techniques. The GND pin
should be tied directly to the ground plane.
The V_CC pin should be bypassed to the ground plane with
a 10µF tantalum capacitor with leads as short as possible.
If the power supply is clean, the LTC1285/LTC1288 can
also operate with smaller 1µF or less surface mount or
ceramic bypass capacitors. All analog inputs should be
referenced directly to the single point ground. Digital
inputs and outputs should be shielded from and/or routed
away from the reference and analog circuitry.
MPU
5V
(e.g. 8051)
3V V_REF
V_CC
P1.4
DIFFERENTIAL INPUTS +IN
CLK
P1.3
COMMON-MODE RANGE
0V TO 3V
–IN
D_OUT
P1.2
GND
CS
LTC1285
LTC1285/88 • F06
Figure 6. Interfacing a 3V Powered LTC1285 to a 5V System
SAMPLE-AND-HOLD
Both the LTC1285 and the LTC1288 provide a built-in
sample-and-hold (S&H) function to acquire signals. The
S&H of the LTC1285 acquires input signals from “+” input
relative to “–” input during the t_SMPL time (see Figure 1).
However, the S&H of the LTC1288 can sample input
signals in the single-ended mode or in the differential
inputs during the t_SMPL time (see Figure 7).
SAMPLE
HOLD
"+" INPUT MUST
SETTLE DURING
THIS TIME
CS
t_SMPL
t_CONV
CLK
D_IN
START
SGL/DIFF
MSBF
DON’T CARE
D_OUT
"+" INPUT
"–" INPUT
B11
1ST BIT TEST "–" INPUT MUST
SETTLE DURING THIS TIME
Figure 7. LTC1288 “+” and “–” Input Settling Windows
LTC1285/88 • F07
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