LTM4601 Datasheet, PDF (14/28 Pages) Linear Technology – 12A DC/DC μModules with PLL, Output Tracking and Margining

LTM4601/LTM4601-1
APPLICATIO S I FOR ATIO
Run Enable
The RUN pin is used to enable the power module. The
pin has an internal 5.1V zener to ground. The pin can be
driven with a logic input not to exceed 5V.
The RUN pin can also be used as an undervoltage lock out
(UVLO) function by connecting a resistor divider from the
input supply to the RUN pin:
V_UVLO
=
R1+ R2
R2
•
1.5V
Power Good
The PGOOD pin is an open-drain pin that can be used to
monitor valid output voltage regulation. This pin monitors
a ±10% window around the regulation point and tracks
with margining.
COMP Pin
This pin is the external compensation pin. The module
has already been internally compensated for most output
voltages. Table 2 is provided for most application require-
ments. A spice model will be provided for other control
loop optimization.
PLLIN
The power module has a phase-locked loop comprised
of an internal voltage controlled oscillator and a phase
detector. This allows the internal top MOSFET turn-on
to be locked to the rising edge of the external clock. The
frequency range is ±30% around the operating frequency
of 850kHz. A pulse detection circuit is used to detect a
clock on the PLLIN pin to turn on the phase lock loop.
The pulse width of the clock has to be at least 400ns and
2V in amplitude. During the start-up of the regulator, the
phase-lock loop function is disabled.
INTV_CC and DRV_CC Connection
An internal low dropout regulator produces an internal
5V supply that powers the control circuitry and DRV_CC
for driving the internal power MOSFETs. Therefore, if
the system does not have a 5V power rail, the LTM4601
can be directly powered by V_IN. The gate driver current
14
through the LDO is about 20mA. The internal LDO power
dissipation can be calculated as:
P_{LDO_LOSS} = 20mA • (V_IN – 5V)
The LTM4601 also provides the external gate driver volt-
age pin DRV_CC. If there is a 5V rail in the system, it is
recommended to connect DRV_CC pin to the external 5V
rail. This is especially true for higher input voltages. Do
not apply more than 6V to the DRV_CC pin. A 5V output can
be used to power the DRV_CC pin with an external circuit
as shown in Figure 16.
Parallel Operation of the Module
The LTM4601 device is an inherently current mode con-
trolled device. Parallel modules will have very good current
sharing. This will balance the thermals on the design.
Figure 19 shows a schematic of the parallel design. The
voltage feedback equation changes with the variable n as
modules are paralleled:
V_OUT
=
0.6V
60.4k
n
+
R_FB
R_FB
η is the number of paralleled modules.
Figure 19 shows an LTM4601 and an LTM4601-1 used in a
parallel design. The 2nd LTM4601 device does not require
the remote sense amplifier, therefore, the LTM4601-1 de-
vice is used. An LTM4601 device can be used without the
diff amp. V_OSNS+ can be tied to ground and the V_OSNS– can
be tied to INTV_CC. DIFFV_OUT can float. When using multiple
LTM4601-1 devices in parallel with an LTM4601, limit the
number to five for a total of six modules in parallel.
Thermal Considerations and Output Current Derating
The power loss curves in Figures 7 and 8 can be used
in coordination with the load current derating curves in
Figures 9 to 14 for calculating an approximate θ_JA for the
module with various heat sinking methods. Thermal models
are derived from several temperature measurements at
the bench and thermal modeling analysis. Thermal Ap-
plication Note 103 provides a detailed explanation of the
analysis for the thermal models and the derating curves.
Tables 3 and 4 provide a summary of the equivalent θ_JA
4601f