LTC6911-2_15 Datasheet, PDF (14/20 Pages) Linear Technology – Dual Matched Amplifiers with Digitally Programmable Gain in MSOP

LTC6911-1/LTC6911-2
PI FU CTIO S
In noise sensitive applications where AGND does not
directly tie to a ground plane, as in Figures 2 and 4, it is
important to AC-bypass the AGND pin. Otherwise, chan-
nel-to-channel isolation is degraded and wideband noise
will enter the signal path from the thermal noise of the
internal voltage divider resistors that present a Thévenin
equivalent resistance of approximately 5kΩ. This noise
can reduce SNR by at least 3dB at high gain settings. An
external capacitor from AGND to the ground plane, whose
impedance is well below 5kΩ at frequencies of interest,
will filter and suppress this noise. A 1µF high quality
capacitor is effective for frequencies down to 1kHz. Larger
capacitors extend this suppression to lower frequencies.
This issue does not arise in dual supply applications
because the AGND pin ties directly to ground.
In applications requiring an analog ground reference other
than half the total supply voltage, the user can override the
built-in analog ground reference by tying the AGND pin to
a reference voltage within the AGND voltage range speci-
fied in the Electrical Characteristics table. The AGND pin
will load the external reference with approximately 5kΩ
returned to the half-supply potential. AGND should still be
capacitively bypassed to a ground plane as noted above.
Do not connect the AGND pin to the V^– pin.
INB (Pin 3): Analog Input. Refer to INA pin description.
G0, G1, G2 (Pins 4, 5, 6): CMOS-Level Digital Gain
Control Inputs. G2 is the most significant bit (MSB) and G0
is the least significant bit (LSB). These pins control the
voltage gain settings for both channels (see Tables 1
and␣ 2). Each channel’s gain cannot be set independent of
the other channel. The logic input pins (G pins) are allowed
to swing from V^– to 10.5V above V^–, regardless of V⁺ so
long as the logic levels meet the minimum requirements
specified in the Electrical Characteristics table. The G0, G1
and G2 pins are high impedance CMOS logic inputs, but
have small pull-down current sources (<10µA) which will
force both channels into the “zero” gain state (digital input
000) if the logic inputs are externally floated. No speed
limitation is associated with the digital logic because it is
memoryless and much faster than the analog signal path.
V^–, V⁺ (Pins 7, 9): Power Supply Pins. The V⁺ and V^– pins
should be bypassed with 0.1µF capacitors to an adequate
analog ground plane using the shortest possible wiring.
Electrically clean supplies and a low impedance ground
are important for the high dynamic range available from
the LTC6911-X (see further details under the AGND pin
description). Low noise linear power supplies are recom-
mended. Switching power supplies require special care to
prevent switching noise coupling into the signal path,
reducing dynamic range.
OUTB (Pin 8): Analog Output. This is the output of the B
channel internal operational amplifier and can swing rail-
to-rail (V⁺ to V^–) as specified in the Electrical Characteris-
tics table. The internal op amp remains active at all times,
including the zero gain setting (digital input 000). For best
performance, loading the output as lightly as possible will
minimize signal distortion and gain error. The Electrical
Characteristics table shows performance at output cur-
rents up to 10mA, and the current limits which occur when
the output is shorted to mid-supply at 2.7V and ±5V
supplies. Signal outputs above 10mA are possible but
current-limiting circuitry will begin to affect amplifier
performance at approximately 20mA. Long-term opera-
tion above 20mA output is not recommended. Do not
exceed a maximum junction temperature of 150°C. The
output will drive capacitive loads up to 50pF. Capacitances
higher than 50pF should be isolated by a series resistor to
preserve AC stability.
OUTA (Pin 10): Analog Output. Refer to OUTB pin
description.
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