LTC3557_15 Datasheet, PDF (14/28 Pages) Linear Technology – USB Power Manager with Li-Ion Charger and Three Step-Down Regulators

LTC3557/LTC3557-1
OPERATION
by the battery via the ideal diodes. The ideal diodes are
fast enough to keep V_OUT from dropping with just the
recommended output capacitor. The ideal diode consists
of a precision amplifier that enables an on-chip P-channel
MOSFET whenever the voltage at V_OUT is approximately
15mV (V_FWD) below the voltage at BAT. The resistance of
the internal ideal diode is approximately 200mΩ. If this is
sufficient for the application, then no external components
are necessary. However, if more conductance is needed,
an external P-channel MOSFET can be added from BAT
to V_OUT.
The GATE pin of the LTC3557/LTC3557-1 drives the gate of
the external P-channel MOSFET for automatic ideal diode
control. The source of the MOSFET should be connected
to V_OUT and the drain should be connected to BAT. Capable
of driving a 1nF load, the GATE pin can control an external
P-channel MOSFET having extremely low on-resistance.
Using the WALL Pin to Detect the Presence of an
External Power Source
The WALL input pin can be used to identify the presence
of an external power source (particularly one that is not
subject to a fixed current limit like the USB V_BUS input).
Typically, such a power supply would be a 5V wall adapter
output or the low voltage output of a high voltage buck
regulator (specifically, LT3480, LT3481 or LT3505). When
the wall adapter output (or buck regulator output) is con-
nected directly to the WALL pin, and the voltage exceeds
the WALL pin threshold, the USB power path (from V_BUS
to V_OUT) will be disconnected. Furthermore, the ACPR pin
will be pulled low. In order for the presence of an external
power supply to be acknowledged, both of the following
conditions must be satisfied:
1. The WALL pin voltage must exceed approximately
4.3V.
2. The WALL pin voltage must exceed 75mV above the
BAT pin voltage.
The input power path (between V_BUS and V_OUT) is
re-enabled and the ACPR pin is pulled high when either
of the following conditions is met:
1. The WALL pin voltage falls to within 25mV of the BAT
pin voltage.
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2. The WALL pin voltage falls below 3.2V.
Each of these thresholds is suitably filtered in time to
prevent transient glitches on the WALL pin from falsely
triggering an event.
See the Applications Information section for an explanation
of high voltage buck regulator control using the V_C pin.
Suspend Mode
When ILIM0 is pulled low and ILIM1 is pulled high the
LTC3557/LTC3557-1 enters Suspend mode to comply
with the USB specification. In this mode, the power path
between V_BUS and V_OUT is put in a high impedance state to
reduce the V_BUS input current to 50μA. If no other power
source is available to drive WALL and V_OUT, the system
load connected to V_OUT is supplied through the ideal diodes
connected to BAT. If an external power source drives WALL
and V_OUT such that V_OUT < V_BUS, the Suspend mode V_BUS
input current can be as high as 200μA.
3.3V Always-On Supply
The LTC3557/LTC3557-1 includes an ultralow quiescent
current low dropout regulator that is always powered. This
LDO can be used to provide power to a system pushbutton
controller or standby microcontroller. Designed to deliver
up to 25mA, the always-on LDO requires a 1μF MLCC
bypass capacitor for compensation. The LDO is powered
from V_OUT, and therefore will enter dropout at loads less
than 25mA as V_OUT falls near 3.3V. If the LDO3V3 output is
not used, it should be disabled by connecting it to V_OUT.
V_BUS Undervoltage Lockout (UVLO)
An internal undervoltage lockout circuit monitors V_BUS
and keeps the input current limit circuitry off until V_BUS
rises above the rising UVLO threshold (3.8V) and at least
50mV above V_OUT. Hysteresis on the UVLO turns off the
input current limit if V_BUS drops below 3.7V or 50mV below
V_OUT. When this happens, system power at V_OUT will be
drawn from the battery via the ideal diode. To minimize the
possibility of oscillation in and out of UVLO when using
resistive input supplies, the input current limit is reduced
as V_BUS drops below 4.45V typical.
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