LTC3545-1_15 Datasheet, PDF (14/20 Pages) Linear Technology – Triple 800mA Synchronous Step-Down Regulator–2.25MHz

LTC3545/LTC3545-1
APPLICATIONS INFORMATION
1. The quiescent current is due to two components: the
DC bias current as given in the electrical characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge, dQ, moves
from PV_IN to ground. The resulting dQ/dt is the current out
of PV_IN that is typically larger than the DC bias current and
proportional to frequency. Both the DC bias and gate charge
losses are proportional to PV_IN and thus their effects will
be more pronounced at higher supply voltages.
2. I²R losses are calculated from the resistances of the
internal switches, R_SW, and external inductor R_L. In con-
tinuous mode, the average output current flowing through
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET R_DS(ON) and the duty cycle (DC) as follows:
R_SW = (R_DS(ON)TOP)(DC) + (R_DS(ON)BOT)(1 – DC)
The R_DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I²R losses, simply add R_SW to
R_L and multiply the result by the square of the average
output current.
Other losses when in switching operation, including C_IN
and C_OUT ESR dissipative losses and inductor core losses,
generally account for less than 2% total additional loss.
Thermal Considerations
The LTC3545/LTC3545-1 requires the package backplane
metal to be well soldered to the PC board. This gives the
QFN package exceptional thermal properties, making
it difficult in normal operation to exceed the maximum
junction temperature of the part. In most applications the
LTC3545/LTC3545-1 do not dissipate much heat due to
their high efficiency. In applications where the LTC3545/
LTC3545-1 are running at high ambient temperature
with low supply voltage and high duty cycles, such as in
dropout, the heat dissipated may exceed the maximum
junction temperature of the part if it is not well thermally
grounded. If the junction temperature reaches approxi-
mately 150°C, the power switches will be turned off and
the SW nodes will become high impedance.
To prevent the LTC3545/LTC3545-1 from exceeding the
maximum junction temperature, the user will need to do
some thermal analysis. The goal of the thermal analysis
is to determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T_R = P_D • θ_JA
where P_D is the power dissipated by the regulator and θ_JA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, T_J, is given by:
T_J = T_A + T_R
where T_A is the ambient temperature.
As an example, consider one channel of the LTC3545/
LTC3545-1 in dropout at an input voltage of 2.5V, a load
current of 800mA, and an ambient temperature of 85°C.
From the typical performance graph of switch resistance,
the R_DS(ON) of the P-channel switch at 85°C can be es-
timated as 0.42Ω. Therefore, power dissipated by the
channel is:
P_D = I_LOAD2 • R_DS(ON) = 0.27W
The θ_JA for the 3mm × 3mm QFN package is 68°C/W. The
temperature rise due to this power dissipation is:
T_R = θ_JA • P_D = 18°C
And a junction temperature of:
T_J = 85°C + 18°C = 103°C
which is below the maximum junction temperature of
125°C. This would not be the case if all three channels
were operating at 800mA in dropout. Then T_R = 55°C,
limiting the allowed ambient temperature in this scenario
to less than 70°C.
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