LTC3446EDE Datasheet, PDF (14/20 Pages) Linear Technology – Monolithic Buck Regulator with Dual VLDO Regulators

LTC3446
applications information
to support the load. The time required for the feedback
loop to respond is dependent on the compensation com-
ponents and the output capacitor size. Typically, 3 to 4
cycles are required to respond to a load step, but only in
the first cycle does the output drop linearly. The output
droop, V_DROOP, is usually about 2 to 3 times the linear
drop of the first cycle. Thus, a good place to start is with
the output capacitor size of approximately:
C_OUTB
≈
2.5
f_O
∆I_OUT
• V_DROOP
More capacitance may be required depending on the duty
cycle and load step requirements.
In most applications, the input capacitor is merely required
to supply high frequency bypassing, since the impedance
to the supply is very low. A 10µF ceramic capacitor is
usually enough for these conditions.
Setting the Buck Converter’s Output Voltage
The buck develops a 0.8V reference voltage between the
feedback pin, BUCKFB, and the signal ground as shown
in Figure 1. The output voltage is set by a resistive divider
according to the following formula:
V_OUTB
≈
0.8V
₁₊
R2 
R1
Keep R1 at or less than 50k. Great care should be taken
to route the BUCKFB line away from noise sources, such
as the inductor or the SW line.
To improve high frequency loop response, a feed forward
capacitor, C_F, can be added as shown in Figure 1. Capacitor
C_F provides phase lead by creating a high frequency zero
with R2, improving phase margin.
Buck Converter Shutdown
The ENBUCK pin enables and shuts down the LTC3446’s
buck converter. Do not leave this pin floating! Tying
ENBUCK to ground disables the buck converter. Bringing
ENBUCK more than 1V above ground enables the buck.
Checking Buck Converter Transient Response
The OPTI-LOOP compensation allows the transient re-
sponse to be optimized for a wide range of loads and
output capacitors. The availability of the I_TH pin not only
allows optimization of the control loop behavior but also
provides a DC coupled and AC filtered closed-loop response
test point. The DC step, rise time and settling at this test
point truly reflects the closed-loop response. Assuming a
predominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin.
The I_TH external components shown in the front page
Typical Application circuit will provide an adequate starting
point for most applications. The series R-C filter sets the
dominant pole-zero loop compensation. The values can
be modified slightly (from 0.5 to 2 times their suggested
values) to optimize transient response once the final PC
layout is done and the particular output capacitor type and
value have been determined. The output capacitors need to
be selected because the various types and values determine
the loop feedback factor gain and phase. An output current
pulse of 20% to 100% of full load current having a rise
time of 1µs to 10µs will produce output voltage and I_TH
pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V_OUTB im-
mediately shifts by an amount equal to ∆I_LOAD • ESR, where
ESR is the effective series resistance of C_OUT. ∆I_LOAD also
begins to charge or discharge C_OUTB generating a feedback
error signal used by the regulator to return V_OUTB to its
steady-state value. During this recovery time, V_OUTB can
be monitored for overshoot or ringing that would indicate
a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with R and
the bandwidth of the loop increases with decreasing C.
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