LTC3374 Datasheet, PDF (14/24 Pages) Linear Technology – 8-Channel Parallelable 1A Buck DC/DCs

LTC3374
OPERATION
Buck Switching Regulators
The LTC3374 contains eight monolithic 1A synchronous
buck switching regulators. All of the switching regula-
tors are internally compensated and need only external
feedback resistors to set the output voltage. The switch-
ing regulators offer two operating modes: Burst Mode
operation (when the MODE pin is set low) for higher
efficiency at light loads and forced continuous PWM mode
(when the MODE pin is set high) for lower noise at light
loads. The MODE pin collectively sets the operating mode
for all enabled buck switching regulators. In Burst Mode
operation at light loads, the output capacitor is charged
to a voltage slightly higher than its regulation point. The
regulator then goes into sleep mode, during which time
the output capacitor provides the load current. In sleep
most of the regulator’s circuitry is powered down, helping
conserve input power. When the output capacitor droops
below its programmed value, the circuitry is powered on
and another burst cycle begins. The sleep time decreases
as load current increases. In Burst Mode operation, the
regulator will burst at light loads whereas at higher loads
it will operate at constant frequency PWM mode operation.
In forced continuous mode, the oscillator runs continu-
ously and the buck switch currents are allowed to reverse
under very light load conditions to maintain regulation.
This mode allows the buck to run at a fixed frequency with
minimal output ripple.
Each buck switching regulator has its own V_IN, SW, FB
and EN pins to maximize flexibility. The enable pins have
two different enable threshold voltages that depend on
the operating state of the LTC3374. With all regulators
disabled, the enable pin threshold is set to 730mV (typical).
Once any regulator is enabled, the enable pin thresholds
of the remaining regulators are set to a bandgap-based
400mV and the EN pins are each monitored by a precision
comparator. This precision EN threshold may be used to
provide event-based sequencing via feedback from other
previously enabled regulators. All buck regulators have
forward and reverse-current limiting, soft-start to limit
inrush current during start-up, and short-circuit protection.
The buck switching regulators are phased in 90° steps to
reduce noise and input ripple. The phase step determines
the fixed edge of the switching sequence, which is when
the PMOS turns on. The PMOS off (NMOS on) phase
is subject to the duty cycle demanded by the regulator.
Bucks 1 and 2 are set to 0°, bucks 3 and 4 are set to 90°,
bucks 5 and 6 are set to 180°, and bucks 7 and 8 are set
to 270°. In shutdown all SW nodes are high impedance.
The buck regulator enable pins may be tied to V_OUT volt-
ages, through a resistor divider, to program power-up
sequencing.
Buck Regulators with Combined Power Stages
Up to four adjacent buck regulators may be combined
in a master-slave configuration by connecting their SW
pins together, connecting their V_IN pins together, and
connecting the higher numbered bucks’ FB pin(s) to the
input supply. The lowest numbered buck is always the
master. In Figure 1, buck regulator 1 is the master. The
feedback network connected to the FB1 pin programs
the output voltage to 1.2V. The FB2 pin is tied to V_IN1-2,
which configures buck regulator 2 as the slave. The SW1
and SW2 pins must be tied together, as must the V_IN1
and V_IN2 pins. The slave buck control circuitry draws no
current. The enable of the master buck (EN1) controls the
V_IN
V_IN1
SW1
BUCK REGULATOR 1
(MASTER)
EN1
FB1
L1
400k
800k
V_IN
V_IN2
SW2
BUCK REGULATOR 2
(SLAVE)
V_IN
EN2
FB2
V_OUT
1.2V
C_OUT ^2A
3374 F01
Figure 1. Buck Regulators Configured as Master-Slave
3374f
14
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