LTC2309_15 Datasheet, PDF (14/26 Pages) Linear Technology – 8-Channel, 12-Bit SAR ADC with IC Interface

LTC2309
Applications Information
Internal Conversion Clock
The internal conversion clock is factory trimmed to
achieve a typical conversion time (t_CONV) of 1.3μs and
a maximum conversion time of 1.8μs over the full
operating temperature range.
I²C Interface
The LTC2309 communicates through an I²C interface.
The I²C interface is a 2-wire open-drain interface sup-
porting multiple devices and multiple masters on a
single bus. The connected devices can only pull the
serial data line (SDA) LOW and can never drive it HIGH.
SDA is required to be externally connected to the sup-
ply through a pull-up resistor. When the data line is not
being driven LOW, it is HIGH. Data on the I²C bus can
be transferred at rates up to 100kbits/s in the standard
mode and up to 400kbits/s in the fast mode. The V_DD
power should not be removed from the LTC2309 when
the I²C bus is active to avoid loading the I²C bus lines
through the internal ESD protection diodes.
Each device on the I²C bus is recognized by a unique
address stored in the device and can only operate either
as a transmitter or receiver, depending on the function
of the device. A device can also be considered as a
master or a slave when performing data transfers. A
master is the device which initiates a data transfer on
the bus and generates the clock signals to permit the
transfer. Devices addressed by the master are consid-
ered slaves.
The LTC2309 can only be addressed as a slave (see
Table 2). Once addressed, it can receive configuration
bits (D_IN word) or transmit the last conversion result. The
serial clock line (SCL) is always an input to the LTC2309
and the serial data line (SDA) is bidirectional. The device
supports the standard mode and the fast mode for data
transfer speeds up to 400kbits/s (see the Timing Diagram
section for definition of the I²C timing).
14
The START and STOP Conditions
Referring to Figure 7, a START (S) condition is gener-
ated by transitioning SDA from HIGH to LOW while
SCL is HIGH. The bus is considered to be busy after the
START condition. When the data transfer is finished, a
STOP (P) condition is generated by transitioning SDA
from LOW to HIGH while SCL is HIGH. The bus is free
after a STOP condition is generated. START and STOP
conditions are always generated by the master.
When the bus is in use, it stays busy if a repeated
START (Sr) is generated instead of a STOP condition.
The repeated START timing is functionally identical to
the START and is used for writing and reading from the
device before the initiation of a new conversion.
START Condition
SDA
S
SCL
STOP Condition
SDA
P
SCL
2309 F07
Figure 7. Timing Diagrams of START and STOP Conditions
Data Transferring
After the START condition, the I²C bus is busy and
data transfer can begin between the master and the
addressed slave. Data is transferred over the bus in
groups of nine bits, one byte followed by one ac-
knowledge (ACK) bit. The master releases the SDA
line during the ninth SCL clock cycle. The slave device
can issue an ACK by pulling SDA LOW or issue a Not
Acknowledge (NACK) by leaving the SDA line high
impedance (the external pull-up resistor will hold the
line high). Change of data only occurs while the SCL
line is LOW.
Data Format
After a START condition, the master sends a 7-bit
address followed by a read/write (R/W) bit. The R/W
bit is 1 for a read request and 0 for a write request.
If the 7-bit address matches one of the LTC2309’s
9 pin-selectable addresses, the ADC is selected. When
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